我正在尝试创建一个避免使用某些c文件的目标。我这样做是因为某些文件不兼容,并希望在构建过程中避免它们。贝娄是我正在使用的方法,但这样做却颇有争议warning: overriding commands for target ...
。我确实了解错误的原因,但不知道解决此问题的更好方法。请指导我,我是MakeFiles的新手。在此先感谢
SRCDIR = ../src
BUILDDIR = build
INCDIR = ../inc
# Compiler to use
CC = gcc
# Include paths for header files
INCLUDES = -I $(INCDIR)
# Compiler flags
# WARNING: Optimization will remove critical code (Problems seen in delay function). Use with caution.
CFLAGS = -Wall -Wextra -g $(INCLUDES) --std=gnu99
CFLAGSNOWARN = -g $(INCLUDES) --std=gnu99
# extra gcc flags used to build dependency files
DEPFLAGS = -MMD -MP
# Paths to required libraries (-L flags)
LFLAGS =
# The specific libraries that project depends on (-l flags)
LIBS = -lreadline -lpthread
# All source files
SRCS = $(wildcard $(SRCDIR)/*.c)
SRCS_1 = $(filter-out $(SRCDIR)/FileToAvoid.c, $(wildcard $(SRCDIR)/*.c))
# All object files
OBJS := $(SRCS:$(SRCDIR)/%.c=%.o)
OBJS_1 := $(SRCS_1:$(SRCDIR)/%.c=%.o)
# name of executable
MAIN = test.exe
# make all
.PHONY: all
# this is the default target
## create temporary .o files and compile main executable
all: $(MAIN)
avoidfile: $(OBJS_1)
@echo "Compiling executable: $(MAIN)"
@$(CC) $(CFLAGS) -o $(MAIN) $(OBJS_1) $(LFLAGS) $(LIBS)
@echo
$(MAIN): $(OBJS)
@echo "Compiling executable: $(MAIN)"
@$(CC) $(CFLAGS) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
@echo
# Automatically builds all object files from source files
# -c option compiles but does not link (create object files)
# -o is output filename
$(OBJS): %.o : $(SRCDIR)/%.c
@echo "Compiling object file: $@"
@$(CC) $(CFLAGS) $(DEPFLAGS) -c $< -o $@
@echo
$(OBJS_1): %.o : $(SRCDIR)/%.c
@echo "Compiling object fileslean: $@"
@$(CC) $(CFLAGS) $(DEPFLAGS) -c $< -o $@
@echo
由于两个要编译的规则都相等,因此可以创建一个规则:
$(sort $(OBJS) $(OBJS_1)): %.o : $(SRCDIR)/%.c
echo "Compiling object file: $@"
$(CC) $(CFLAGS) $(DEPFLAGS) -c $< -o $@
sort
函数将删除重复项,并且即使您不关心排序,也建议为此而建议。
您可能认为双冒号规则可能会有所帮助,但请注意!这些配方的执行是[[all,导致同一来源的多次编译。