如何从 Chisel 生成 Verilog 而不是 SystemVerilog？

Question

这是我的 GCD.scala

package gcd

import chisel3._

class GCD extends Module {
  val io = IO(new Bundle {
    val value1        = Input(UInt(16.W))
    val value2        = Input(UInt(16.W))
    val loadingValues = Input(Bool())
    val outputGCD     = Output(UInt(16.W))
    val outputValid   = Output(Bool())
  })

  val x = Reg(UInt())
  val y = Reg(UInt())

  when(x > y) { x := x - y }.otherwise { y := y - x }

  when(io.loadingValues) {
    x := io.value1
    y := io.value2
  }

  io.outputGCD   := x
  io.outputValid := y === 0.U
}

object Elaborate extends App {
  val firtoolOptions = Array("--lowering-options=" + List(
    "disallowLocalVariables",
    "disallowPackedArrays",
    "locationInfoStyle=wrapInAtSquareBracket"
  ).reduce(_ + "," + _))
  circt.stage.ChiselStage.emitSystemVerilogFile(new gcd.GCD(), args, firtoolOptions)
}

我正在使用 Chisel 6.4.0:

ivy"org.chipsalliance::chisel:6.4.0"
ivy"org.chipsalliance:::chisel-plugin:6.4.0"
ivy"edu.berkeley.cs::chiseltest:6.0.0"

Chisel 6 似乎默认会发出 systemverilog。

当我切换到 Chisel 3 时，getVerilogString() 对于生成 verilog 很有用，但它也会从 Chisel 6.4.0 生成 systemverilog。

我找了很多解决方案，都是基于Chisel 3解决的。

如何从 Chisel 6.4.0 生成 verilog？

Answer 1

试试这个：

import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}

object GenerateVerilog extends App {
  (new chisel3.stage.ChiselStage).execute(
    Array("-X", "verilog", "--target-dir", "verilog_output"),
    Seq(ChiselGeneratorAnnotation(() => new gcd.GCD()))
  )
}