system-verilog 相关问题

module apb_mod #(parameter BW = 8, CSR_no = 4)( //////// APB signals //////// input wire pclk, /// clock input wire presetn, /// active low synchronous reset input wire [BW-1:0] paddr, /// address input wire psel, /// peripheral select input wire penable, /// peripheral enable input wire pwrite, /// peripheral write input wire [BW-1:0] pwdata, /// peripheral data output wire pready, /// peripheral ready output wire [BW-1:0] prdata, /// peripheral read data input wire pwakeup, /// peripheral wakeup output wire pslverr, ////////// dummy UART CSRs in ping pong ////////// input wire done, output wire enable_O, output wire r_w_O, output wire [3:0] buad_rate_O, output wire [3:0] trans_count_O, output wire [3:0] sl_address_O ); ////////////// APB REGs //////// reg [2:0] state, next_state; reg pready_reg; reg pslverr_reg; reg [BW-1:0] prdata_reg; ////////////////// pingpong Registers ////// reg [7:0] s_reg [1:0]; reg [7:0] d_reg_0[3:0]; reg [7:0] d_reg_1[3:0]; /////////////// states of APB ///////////////////// localparam IDLE = 3'b000, SETUP = 3'b001, ACCESS = 3'b010; /// states of APB ///////////////////////// uart C S R regs ////////// reg enable_O_reg; reg r_w_O_reg; reg [3:0] buad_rate_O_reg; reg [3:0] trans_count_O_reg; reg [3:0] sl_address_O_reg; /////////////////////// assignment ///////////////////////////// assign enable_O = enable_O_reg; assign r_w_O = r_w_O_reg; assign buad_rate_O = buad_rate_O_reg; assign trans_count_O = trans_count_O_reg; assign sl_address_O = sl_address_O_reg; assign prdata = prdata_reg; assign pslverr = pslverr_reg; always @(posedge pclk) begin if (!presetn) begin s_reg[0][0] <= 1; // s_status s_reg[0][1] <= 0; // producer s_reg[0][2] <= 0; // consumer d_reg_0[0][0] <= 0; // enb_0 d_reg_1[0][0] <= 0; // enb_1 state <= IDLE; pslverr_reg <= 0; end else begin state <= next_state; end end always @(*) begin if (s_reg[0][2] == 0) begin enable_O_reg = d_reg_0[0][1]; r_w_O_reg = d_reg_0[0][2]; buad_rate_O_reg = d_reg_0[1]; trans_count_O_reg = d_reg_0[2]; sl_address_O_reg = d_reg_0[3]; end else if (s_reg[0][2] == 1) begin enable_O_reg = d_reg_1[0][1]; r_w_O_reg = d_reg_1[0][2]; buad_rate_O_reg = d_reg_1[1]; trans_count_O_reg = d_reg_1[2]; sl_address_O_reg = d_reg_1[3]; end else begin enable_O_reg = d_reg_0[0][1]; r_w_O_reg = d_reg_0[0][2]; buad_rate_O_reg = d_reg_0[1]; trans_count_O_reg = d_reg_0[2]; sl_address_O_reg = d_reg_0[3]; end end always @(posedge pclk) begin if (done) begin if (d_reg_0[0][0] == 1 & d_reg_1[0][0] == 0) begin d_reg_0[0][0] <= 0; s_reg[0][2] <= 0; end else if (d_reg_0[0][0] == 0 & d_reg_1[0][0] == 1) begin d_reg_1[0][0] <= 0; s_reg[0][2] <= 1; end else begin s_reg[0][2] <= 0; end end end always @(posedge pclk) begin if (penable) begin if (pwrite) begin case (s_reg[0][1]) 1'b0: begin if (paddr == 8'hf0) s_reg[0][1] <= pwdata[0]; else begin d_reg_0[paddr] <= pwdata; s_reg[0][2] <= 1; s_reg[0][0] <= 0; end end 1'b1: begin if (paddr == 8'hf0) s_reg[0][1] <= pwdata[0]; else begin d_reg_1[paddr] <= pwdata; s_reg[0][2] <= 0; s_reg[0][0] <= 0; end end default: begin d_reg_0[paddr] <= pwdata; s_reg[0][0] <= 1; pslverr_reg <= 1; end endcase end else begin prdata_reg <= (paddr[7:4] == 4'hf) ? s_reg[0][2:0] : (paddr[7:4] == 4'he) ? d_reg_0[paddr[3:0]] : d_reg_1[paddr[3:0]]; end end end always @(*) begin case (state) IDLE: next_state = psel ? SETUP : IDLE; SETUP: next_state = penable ? ACCESS : SETUP; ACCESS: next_state = (psel && pready) ? SETUP : (!psel ? IDLE : ACCESS); default: next_state = IDLE; endcase end endmodule //////////////////////Interface////////////////////// interface top_if (); logic [7 : 0]paddr; // 8-bit logic [7 : 0]pwdata; // 8-bit logic [7 : 0]prdata; // 8-bit logic pwrite; // 1-bit logic psel; // 1-bit logic penable; // 1-bit logic presetn; // 1-bit logic pclk; // 1-bit logic pslverr; // 1-bit logic pwakeup; // 1-bit logic pready; // 1-bit logic enable_O; // 1-bit logic r_w_O; // 1-bit logic [3:0] buad_rate_O; // 4-bit logic [3:0]trans_count_O;// 4-bit logic [3:0]sl_address_O; // 4-bit endinterface

verilog system-verilog uvm test-bench edaplayground

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匿名结构导出到top

struct verilog system-verilog register-transfer-level

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我正在SystemVerilog中工作4深，8位宽的FIFO。我已经写了FIFO模块和TestBench，但是我在数据读取操作和标志更新中遇到了意外的行为。

Test 1: Writing data to FIFO Write Data: 00, Full: 0, Empty: 1 Write Data: 01, Full: 0, Empty: 1 Write Data: 02, Full: 0, Empty: 0 Write Data: 03, Full: 0, Empty: 0 Test 2: Reading data from FIFO Read Data: xx, Full: 0, Empty: 0 Read Data: 00, Full: 0, Empty: 0 Read Data: 01, Full: 1, Empty: 0 Read Data: 02, Full: 0, Empty: 0 Test 3: Simultaneous read and write Write Data: 04, Read Data: 03, Full: 0, Empty: 1 Write Data: 05, Read Data: 03, Full: 0, Empty: 1 Write Data: 06, Read Data: 03, Full: 0, Empty: 0 Write Data: 07, Read Data: 03, Full: 0, Empty: 0 Test 4: Testing FIFO full condition Write Data: 08, Full: 0, Empty: 0 Write Data: 09, Full: 0, Empty: 0 Write Data: 0a, Full: 1, Empty: 0 Write Data: 0b, Full: 0, Empty: 0 Write Data: 0c, Full: 0, Empty: 0 Test 5: Testing FIFO empty condition Read Data: 03, Full: 0, Empty: 0 Read Data: 0b, Full: 0, Empty: 0 Read Data: 0c, Full: 0, Empty: 0 Read Data: 08, Full: 0, Empty: 0 Read Data: 09, Full: 1, Empty: 0 Simulation completed.

verilog system-verilog fifo test-bench

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Verilog LRM 23.3.3.1将输出连接到输出

从LRM： 23.3.3.1端口胁迫一个被声明为输入（输出）但用作输出（输入）或INOUT的端口，可以强制胁迫到INOUT。如果不被强迫到INOUT，应发出警告。

verilog system-verilog iverilog

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如何定义枚举类型并将其包含在多个模块中？我想定义用于功能代码的枚举类型，然后将其包含在多个模块中。但是，当我尝试使用modelsim编译解决方案时，我会收到以下错误：康恩...

Connection类型'枚举reg [2：0]'与'enum reg [2：0]'' 对于端口（function_code）：枚举类型必须匹配。

verilog system-verilog

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我经常使用$ display，$误差，$ systemverilog中的致命功能来显示各种数字值。例如，在使用QuestA时，以下内容将正确显示输出到

system-verilog quartus