我的 verilog 代码出现此错误，“常量表达式的非法操作”

Question

每当我编译此代码时，都会收到以下错误。

module mv2_generate
(
    input [127:0] c_array [1:0],
    input [127:0] p_array [1:0],
    input [127:0] p1_array [1:0],
    output reg [15:0] min_mv
);

   //genvar index;
   integer a, b, index, m;
  //genvar m;
  // a= (m*7)+m+7;
  // b= (m*7)+m;

   reg [7:0] read_dataC;  //registers for C,P,P'
   reg [7:0] read_dataP;
   reg [7:0] read_dataP1;
   reg [15:0] out_pe0;
   reg pe0_en;
   pe PE0(.a(read_dataC),.b(read_dataP),.en(pe0_en),.pe_out(out_pe0));

always @*
begin
//generate
   for (index=0; index<2; index=index+1)
    begin
    // assign  n=n+1;
    //  a=7;
    //  b=0;


      for (m=0; m<16; m=m+1)
      begin
       if(index<2)
        begin
         if (m>=0)
          begin
           read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
           read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
           // read_dataC = c_array [index] [a:b];
          // read_dataP = p_array [index] [a:b];
          #50;
          $display("pe out: %d",out_pe0);
          //pe PE0(read_dataC, read_dataP, out_pe0);
         end

       // a= a+8;
       // b= b+8;
       end
      end
    end
  end
//endgenerate

     //assign min_mv= out_pe0;

endmodule 

 // 
 module pe(input [7:0] a, input [7:0] b, input en, output reg [7:0] pe_out);
       //reg [15:0] acc_temp = acc;
        always @* begin
        //$display("End of Sim: %d", en);
         if(en) begin
               if (a<b) begin
                        assign pe_out = b - a;
                 end
                 else if (a==b) begin
                       assign pe_out = 8'd0;
                 end
                 else begin
                       assign pe_out = a - b;
                 end
                 //acc_temp = acc_temp + pe_out;
                 //acc = acc_temp;
                  //$display("End of Sim: %d", acc);
             end
             else begin
              pe_out = 8'd0;
             end
             end
        endmodule

错误

ncverilog(64): 15.20-s029: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
file: mv2test.v
           read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
                                          |
ncvlog: *E,NOTPAR (mv2test.v,38|42): Illegal operand for constant expression [4(IEEE)].
           read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
                                               |
ncvlog: *E,NOTPAR (mv2test.v,38|47): Illegal operand for constant expression [4(IEEE)].
           read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
                                                    |
ncvlog: *E,NOTPAR (mv2test.v,38|52): Illegal operand for constant expression [4(IEEE)].
           read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
                                                         |
ncvlog: *E,NOTPAR (mv2test.v,38|57): Illegal operand for constant expression [4(IEEE)].
           read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
                                          |
ncvlog: *E,NOTPAR (mv2test.v,39|42): Illegal operand for constant expression [4(IEEE)].
           read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
                                               |
ncvlog: *E,NOTPAR (mv2test.v,39|47): Illegal operand for constant expression [4(IEEE)].
           read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
                                                    |
ncvlog: *E,NOTPAR (mv2test.v,39|52): Illegal operand for constant expression [4(IEEE)].
           read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
                                                         |
ncvlog: *E,NOTPAR (mv2test.v,39|57): Illegal operand for constant expression [4(IEEE)].
    module worklib.mv2_generate:v
        errors: 8, warnings: 0
module pe(input [7:0] a, input [7:0] b, input en, output reg [7:0] pe_out);
        |
ncvlog: *W,RECOME (mv2test.v,83|8): recompiling design unit worklib.pe:v.
    First compiled from line 59 of mv2test.v.
ncverilog: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 1).

Answer 1

这在 Verilog（和 SystemVerilog）中是非法的：

c_array [index] [(m*7)+m+7:(m*7)+m];

具体来说，在

part select

中，: 的右侧不能有变量。相反，你需要这样写：

c_array [index] [(m*7)+m+7 -: 8];

或者这个：

c_array [index] [(m*7)+m +: 8];

-:

和

+:

运算符左侧的值是起始索引。右侧的数字是宽度。这必须是恒定的。因此，你的错误。

-:

运算符从起始索引开始倒数；

+:

运算符进行加计数。原始数组声明的方向并不重要：无论数组的方向如何，您都可以使用任一运算符。

Answer 2

问题是，在verilog中，在此上下文中使用的位切片或部分选择表达式需要常量（编译时）表达式，但您尝试使用不是常量的表达式：

(m*7)+m+7

和

(m*7)+m

。在verilog中，像

m

这样的循环变量和动态计算不能直接用于位选择。

要解决此问题，您可以在循环内预先计算索引，然后使用这些预先计算的索引进行位选择。以下是重构该部分的方法：

integer start_idx, end_idx;

for (index = 0; index < 2; index = index + 1) begin
    for (m = 0; m < 16; m = m + 1) begin
        start_idx = (m * 8);
        end_idx = start_idx + 7;
        
        read_dataC = c_array[index][end_idx:start_idx];
        read_dataP = p_array[index][end_idx:start_idx];
        
        #50;
        $display("pe out: %d", out_pe0);
    end
end