带有numeric_std的结构加法器（2种）

Question

我具有以下VHDL代码以使用结构体系结构实现加法器，因此首先我必须在两个.vhd文件中使用软件包numeric_std进行基本加法器：

这是adder.vhd

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;

entity adder is
generic(
                g_width : natural := 32);
port(
            cin : in std_logic;
            op1 : in std_logic_vector (g_width-1 downto 0);
            op2 : in std_logic_vector (g_width-1 downto 0);
            add : out std_logic_vector (g_width downto 0));
end adder;

然后是rtl.vhd：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

architecture rtl of adder is

begin

   add <= std_logic_vector(resize(unsigned(op1), g_width+1) + resize(unsigned(op2), g_width+1) + unsigned'(0=>cin));
end rtl;

这里一切都很好，但是我必须制作另一个加法器（cpa.vhd，它使用新的enitty fa.vhd（这是一个新文件）的实例具有加法器的体系结构所以这是代码：

fa.vhd：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fa is
port(   ope1 : in std_logic;
        ope2 : in std_logic;
        cin : in std_logic;
        cout : out std_logic;
        sum : out std_logic);
end entity fa;

cpa.vhd：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

architecture cpa of adder is

component fa is 
port(   ope1 : in std_logic;
        ope2 : in std_logic;
        cin : in std_logic;
        cout : out std_logic;
        sum : out std_logic);
end component;
signal carry : std_logic_vector(g_width downto 0);

begin

p_cpa : for i in 0 to g_width-1 generate
    i_fa : fa port map(
                            ope1=>op1(i),
                            ope2=>op2(i),
                            cin=>carry(i),
                            sum=>add(i),
                            cout=>carry(i+1));
end generate p_cpa;
end cpa;

所以问题是它不起作用，当我运行tb时，它似乎是未签名的：

我不知道问题出在哪里。

我忘记了结核病：

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity tb_adder is
end tb_adder;

architecture beh of tb_adder is
  constant c_width : natural := 32;
  constant c_upper_bound : natural := (2**16)-1;
  component adder
    generic(
      g_width : natural := 16
      );
    port(
      cin : in  std_logic;
      op1 : in  std_logic_vector(g_width-1 downto 0);
      op2 : in  std_logic_vector(g_width-1 downto 0);
      add : out std_logic_vector(g_width downto 0)
      );
  end component;

-- Inputs
  signal cin : std_logic;
  signal op1 : std_logic_vector(c_width-1 downto 0) := (others => '0');
  signal op2 : std_logic_vector(c_width-1 downto 0) := (others => '0');

-- Outputs
  signal res      : std_logic_vector(c_width downto 0);
  signal res_xpct : std_logic_vector(c_width downto 0);


begin
--Instance 
  dut : adder generic map (
    g_width => c_width
     )
     port map (
    cin => cin,
    op1 => op1,
    op2 => op2,
    add => res
    );

  cin <= '0';

  p_stim : process
    variable v_i : natural := 0;
    variable v_j : natural := 0;
  begin
    i_loop : for v_i in 0 to c_upper_bound loop
      j_loop : for v_j in 0 to c_upper_bound loop
        op1      <= std_logic_vector(to_unsigned(v_i, c_width));
        op2      <= std_logic_vector(to_unsigned(v_j, c_width));
        res_xpct <= std_logic_vector(to_unsigned(v_i + v_j, c_width+1));
        wait for 10 ns;
        assert res = res_xpct
          report "Error: wrong operation"
          severity error;
        wait for 10 ns;
      end loop j_loop;
    end loop i_loop;
    wait;
  end process p_stim;

end beh;

谢谢您的回答。

Answer 1

所以我编写了一个有效的fa架构和一个测试平台，并对cpa架构进行了几处更改：

architecture foo of fa is       -- added architecture
begin
    sum <= ope1 xor ope2 xor cin;
    cout <= (ope1 and ope2) or
            (ope1 and cin) or
            (ope2 and cin);
end architecture;

architecture cpa of adder is

    component fa is 
        port (   
            ope1:  in  std_logic;
            ope2:  in  std_logic;
            cin:   in  std_logic;
            cout:  out std_logic;
            sum:   out std_logic
        );
    end component;

    signal carry:  std_logic_vector(g_width downto 0);

begin
    carry(0) <= cin;  -- added hook up the carry in
p_cpa:  
    for i in 0 to g_width-1 generate
i_fa:  
    fa 
        port map (
            ope1 => op1(i),
            ope2 => op2(i),
            cin => carry(i),
            sum => add(i),
            cout => carry(i+1)
        );
    end generate p_cpa;
    add(g_width) <= carry(g_width);  -- added hook up the carry out to the MSB
end architecture cpa;

对cpa架构的更改仅将cin分配给carry(0，将carry(32)分配给add(32)，即构建与rtl架构兼容的加法器的想法；

测试台同时练习两种体系结构：

library ieee;
use ieee.std_logic_1164.all;

entity adder_tb is
end entity;

architecture foo of adder_tb is
    constant g_width:   natural := 32;
    signal cin:         std_logic;
    signal op1:         std_logic_vector (g_width - 1 downto 0);
    signal op2:         std_logic_vector (g_width - 1 downto 0);
    signal add_rtl:     std_logic_vector (g_width downto 0);
    signal add_cpa:     std_logic_vector (g_width downto 0);
begin

DUT_rtl:
    entity work.adder (rtl)
        generic map (g_width)
        port map (
            cin => cin,
            op1 => op1,
            op2 => op2,
            add => add_rtl
        );

DUT_cpa:
    entity work.adder (cpa)
        generic map (g_width)
        port map (
            cin => cin,
            op1 => op1,
            op2 => op2,
            add => add_cpa
        );

STIMULUS:
    process
    begin
        wait for 10 ns;
        cin <= '0';
        op1 <= x"feedface";
        op2 <= x"deadbeef";
        wait for 10 ns;
        cin <= '1';
        wait for 10 ns;
        wait;
    end process;

end architecture;

这给了我们：

两个加法器上的结果相同，这说明我们对体系结构cpa所做的两个更改是正确的。

您的问题中没有足够的信息来确定为什么波形上的输入都是'U'。

在我写的小测试台中，这些是在STIMULUS进程中分配的。

我的64位程序员计算器说结果正确。