位旋转时出现Verilog“不是常数”错误

Question

我有这段代码。我试图将WNext旋转data_fromRAM的低4位。

input clk, rst;

input wire [15:0] data_fromRAM;
output reg [15:0] data_toRAM;
output reg wrEn;

// 12 can be made smaller so that it fits in the FPGA
output reg [12:0] addr_toRAM;
output reg [12:0] PC; // This has been added as an output for TB purposes
output reg [15:0] W; // This has been added as an output for TB purposes

reg [12:0] PCNext;
reg [ 2:0] opcode, opcodeNext,state, stateNext;
reg [12:0] operand, operandNext;
reg [15:0] num, numNext, WNext;

if(data_fromRAM < 16) WNext = W >> data_fromRAM;
else if (data_fromRAM > 16 & data_fromRAM < 31) WNext = W << data_fromRAM[3:0];
else if (data_fromRAM > 32 & data_fromRAM > 47) WNext = {W[data_fromRAM[3:0] - 1:0], W[15:data_fromRAM[3:0]]};
else WNext = {W[15 - data_fromRAM[3:0]:0], W[15:16 - data_fromRAM[3:0]]};

但是我遇到了错误：

data_fromRAM不是常数。

如何解决此错误？有没有一种方法可以将data_fromRAM复制到常量变量中，然后执行操作？还是应该采用其他方法？

注意：输出寄存器[15：0] datatoRAM;

编辑：

always @*begin
    WNext = W;
    PCNext = PC;
    stateNext    = state;
    opcodeNext   = opcode;
    operandNext = operand;
    numNext     = num;
    addr_toRAM   = 0;
    wrEn         = 0;
    data_toRAM   = 0;
//here I have if(rst)
else 
    case(state)
//other cases
        2: begin
            PCNext = PC + 1;
            WNext = W;
            opcodeNext   = opcode;
            operandNext = operand;
            addr_toRAM   = 0;
            numNext     = data_fromRAM;
            wrEn         = 0;
            data_toRAM   = 0;
            stateNext    = 0;
            case (opcodeNext)
                ... //I excluded other cases
                3'b010: begin //SRRL
                    if(data_fromRAM < 16) WNext = W >> data_fromRAM;
                    else if (data_fromRAM > 16 & data_fromRAM < 31) WNext = W << data_fromRAM[3:0];
                    else if (data_fromRAM > 32 & data_fromRAM > 47) WNext = {W[data_fromRAM[3:0] - 1:0], W[15:data_fromRAM[3:0]]};
                    else WNext = {W[15 - data_fromRAM[3:0]:0], W[15:16 - data_fromRAM[3:0]]};
                end

Answer 1

我认为基于data_fromRAM的值，您正在尝试“加扰” W中的数据。假设WNext也是16位变量，则可以使用：

if(data_fromRAM < 16) 
    WNext = W >> data_fromRAM;
else if (data_fromRAM > 16 & data_fromRAM < 31) 
    WNext = W << data_fromRAM[3:0];
else if (data_fromRAM > 32 & data_fromRAM > 47) 
    WNext = (W << (16-data_fromRAM[3:0])) | (W >> data_fromRAM[3:0]);
else 
    WNext = (W << data_fromRAM[3:0]) | (W >> (16-data_fromRAM[3:0]));

Answer 2

如错误消息所示，位选择表达式必须具有一个恒定值。在详细说明/编译时，外括号中的表达式必须为常数：

W[15 - data_fromRAM[3:0]:0]

您不能将变量data_fromRAM复制到常量中。

我相信您需要一种不同的方法，但是很难从所展示的内容中知道您要做什么。

而且，这是一个错误：

else if (data_fromRAM > 32 & data_fromRAM > 47)

我认为您打算使用< 47：

else if (data_fromRAM > 32 & data_fromRAM > 47)