如何使用verilator运行testbench.v

Question

我在GitHub上找到了一个RISCV项目（这是该项目），并尝试使用verilator运行该项目的testbench.v文件。但是，在过程中遇到了错误。

我的

Workspace

是：

../
├── CHIP.v
├── README.md
├── VCPU.v
├── WIN.sdf
├── WIN.v
├── WIN_syn.v
├── area_CPU.out
├── sim
│   ├── Makefile
│   ├── dat
│   │   ├── Fibonacci_instruction.txt
│   │   ├── Foutput.txt
│   │   ├── golden.dat
│   │   └── instruction2.txt
│   ├── include
│   │   ├── add.h
│   │   └── verilated.h
│   └── src
│       └── testbench.v
├── src
│   ├── ALU.v
│   ├── ALU_Control.v
│   ├── Adder.v
│   ├── CPU.v
│   ├── Control.v
│   ├── DataMemory.v
│   ├── EX_MEM.v
│   ├── ForwardingMUX.v
│   ├── ForwardingUnit.v
│   ├── HazardDetect.v
│   ├── ID_EX.v
│   ├── IF_ID.v
│   ├── Instruction_Memory.v
│   ├── MEM_WB.v
│   ├── MUX32.v
│   ├── MUX_Control.v
│   ├── PC.v
│   ├── Registers.v
│   ├── Sign_Extend.v
│   ├── VALU.v
│   ├── VALU_ctrl.v
│   ├── VControl.v
│   ├── VEX_MEM.v
│   └── shift2.v
└── syn.src

我克隆了该项目并编写了一个

Makefile

：

TOP_NAME := CPU
SRC_DIR  := ../src/
SRC_FILE := $(shell find $(SRC_DIR) -name '*.vh') $(shell find $(SRC_DIR) -name '*.svh') $(shell find $(SRC_DIR) -name '*.v') $(shell find $(SRC_DIR) -name '*.sv')

.PHONY: run clean

obj_dir/V$(TOP_NAME): src/* $(SRC_FILE)
    verilator -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP -exe --trace --trace-structs --build --timing src/testbench.v $(SRC_FILE) -I$(SRC_DIR) --top $(TOP_NAME) -j `nproc`

run: obj_dir/V$(TOP_NAME)
    ./obj_dir/V$(TOP_NAME)

clean:
    rm -rf obj_dir

之后，当我在终端中输入

make

尝试编译文件时，发生了错误：

verilator -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP -exe --trace --trace-structs --build --timing src/testbench.v   ../src/shift2.v ../src/Instruction_Memory.v ../src/EX_MEM.v ../src/ForwardingUnit.v ../src/Registers.v ../src/CPU.v ../src/ForwardingMUX.v ../src/VEX_MEM.v ../src/VALU_ctrl.v ../src/HazardDetect.v ../src/MEM_WB.v ../src/IF_ID.v ../src/VALU.v ../src/ALU.v ../src/DataMemory.v ../src/MUX32.v ../src/Control.v ../src/Adder.v ../src/ID_EX.v ../src/VControl.v ../src/PC.v ../src/MUX_Control.v ../src/Sign_Extend.v ../src/ALU_Control.v  -I../src/ --top CPU -j `nproc`
make[1]: Entering directory '/home/chris/Code/graduation-project/sim/obj_dir'
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++17 -Os -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++17 -Os -c -o verilated_vcd_c.o /usr/local/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VCPU.cpp VCPU___024root__DepSet_h6c062b6c__0.cpp VCPU___024root__DepSet_h295dba0a__0.cpp VCPU__Trace__0.cpp VCPU__ConstPool_0.cpp VCPU___024root__Slow.cpp VCPU___024root__DepSet_h6c062b6c__0__Slow.cpp VCPU___024root__DepSet_h295dba0a__0__Slow.cpp VCPU__Syms.cpp VCPU__Trace__0__Slow.cpp > VCPU__ALL.cpp
echo "" > VCPU__ALL.verilator_deplist.tmp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++17 -Os -c -o VCPU__ALL.o VCPU__ALL.cpp
Archive ar -rcs VCPU__ALL.a VCPU__ALL.o
g++    verilated.o verilated_vcd_c.o VCPU__ALL.a      -o VCPU
/usr/bin/ld: /usr/lib/gcc/x86_64-linux-gnu/11/../../../x86_64-linux-gnu/Scrt1.o: in function `_start':
(.text+0x1b): undefined reference to `main'
collect2: error: ld returned 1 exit status
make[1]: *** [VCPU.mk:61: VCPU] Error 1
rm VCPU__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/chris/Code/graduation-project/sim/obj_dir'
%Error: make -C obj_dir -f VCPU.mk -j 20 exited with 2
%Error: Command Failed /usr/local/bin/verilator_bin -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP -exe --trace --trace-structs --build --timing src/testbench.v ../src/shift2.v ../src/Instruction_Memory.v ../src/EX_MEM.v ../src/ForwardingUnit.v ../src/Registers.v ../src/CPU.v ../src/ForwardingMUX.v ../src/VEX_MEM.v ../src/VALU_ctrl.v ../src/HazardDetect.v ../src/MEM_WB.v ../src/IF_ID.v ../src/VALU.v ../src/ALU.v ../src/DataMemory.v ../src/MUX32.v ../src/Control.v ../src/Adder.v ../src/ID_EX.v ../src/VControl.v ../src/PC.v ../src/MUX_Control.v ../src/Sign_Extend.v ../src/ALU_Control.v -I../src/ --top CPU -j 20
make: *** [Makefile:8: obj_dir/VCPU] Error 2

这似乎是一个编译问题，但我不确定如何解决它。谁能建议采取什么步骤？我对 verilator 还很陌生 😭😭btw，我的 verilator 版本是 Verilator 5.002 2022-10-29 rev v5.002

Answer 1

您无法使用 Verilator 模拟测试平台 Verilog 代码。

Verilator 是非常具体的模拟器，仅适用于可合成的代码。它无法像 testbench.v

中那样管理延迟指令。

我需要开源 Verilog 模拟器，请使用

Icarus Verilog 尝试一下。