在chisel6.2.0中，如何使用hex文件来初始化内存并测试它？

Question

我有同样的问题这个：in-chisel-3-how-to-initialize-memory-test-code-with-text-file，我的测试代码表明 loadMemoryFromFile 没有意义。我认为我的文件路径是正确的，但它不起作用。
我用的是chisel6.2.0。这是我的项目的结构：

example
└── src
│   └── hex
│   │   └── example.hex.txt
│   └── main/scala/circuit
│   │             └── IMemory.scala
│   └── test/scala/circuit
│                 └── IMemorySpec.scala
└--build.sbt

build.sbt

ThisBuild / scalaVersion := "2.13.12"
ThisBuild / version := "0.1.0"
ThisBuild / organization := "%ORGANIZATION%"

val chiselVersion = "6.2.0"

lazy val root = (project in file("."))
  .settings(
    name := "%NAME%",
    libraryDependencies ++= Seq(
      "org.chipsalliance" %% "chisel" % chiselVersion,
      "org.scalatest" %% "scalatest" % "3.2.16" % "test"
    ),
    scalacOptions ++= Seq(
      "-language:reflectiveCalls",
      "-deprecation",
      "-feature",
      "-Xcheckinit",
      "-Ymacro-annotations"
    ),
    addCompilerPlugin(
      "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full
    )
  )

示例.hex.txt

003100b3
40628033
06432283
06512423
064000ef

IMemory.scala

package circuit

import chisel3._
import chisel3.util.experimental.loadMemoryFromFileInline
import circt.stage.ChiselStage

class IMemoryIO extends Bundle {
  val rdAddr = Input(UInt(5.W))
  val rdData = Output(UInt(32.W))
  val wrAddr = Input(UInt(5.W))
  val wrData = Input(UInt(32.W))
  val wrEna = Input(UInt(1.W))
}

class IMemory(memoryFile: String = "") extends Module {
  val io = IO(new IMemoryIO)
  val mem = SyncReadMem(1024, UInt(32.W))
  io.rdData := mem.read(io.rdAddr)
  io.rdData := mem(io.rdAddr)
  when(io.wrEna === 1.U) {
    mem.write(io.wrAddr, io.wrData)
  }
  if (memoryFile.trim().nonEmpty) {
    loadMemoryFromFileInline(mem, memoryFile)
  }
}

IMemorySpec.scala

package circuit
import chisel3._
import chisel3.experimental.BundleLiterals._
import chisel3.simulator.EphemeralSimulator._
import org.scalatest.freespec.AnyFreeSpec
import org.scalatest.matchers.must.Matchers
import java.io.File
class IMemorySpec extends AnyFreeSpec with Matchers {
  "write memory" in {
    simulate(new IMemory("src/hex/example.hex.txt")) { dut =>
      dut.io.wrAddr.poke(4.U)
      dut.io.wrEna.poke(1.U)
      dut.io.wrData.poke(0x003100b3.U)
      dut.clock.step()
      dut.io.rdAddr.poke(4.U)
      dut.clock.step()
      dut.io.rdData.expect(0x003100b3.U)
    }
  }
  "loadMemory from file" in {
    simulate(new IMemory("src/hex/example.hex.txt")) { dut =>
      dut.io.rdAddr.poke(0.U)
      dut.clock.step()
      dut.io.rdData.expect(0x003100b3.U)
    }
  }
}

当我运行

sbt "testOnly circuit.IMemorySpec

时，输出是：

[info] - file should exist
[info] - write memory
[info] - loadMemory from file *** FAILED ***
[info]   chisel3.simulator.PeekPokeAPI$FailedExpectationException: Failed Expectation: Observed value '0' != 3211443. Expectation failed: observed value 0 != 3211443

Observed value '0' != 3211443.

。我无法读取我期望的数据。

我可以确定这不是路径错误。因为当我使用chisel5.1.0和chiseltest时，它可以工作。 这是我的 build.sbt。

// See README.md for license details.

ThisBuild / scalaVersion := "2.13.12"
ThisBuild / version := "0.1.0"
ThisBuild / organization := "%ORGANIZATION%"

val chiselVersion = "5.1.0"

lazy val root = (project in file("."))
  .settings(
    name := "%NAME%",
    libraryDependencies ++= Seq(
      "org.chipsalliance" %% "chisel" % chiselVersion,
      "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test"
    ),
    scalacOptions ++= Seq(
      "-language:reflectiveCalls",
      "-deprecation",
      "-feature",
      "-Xcheckinit",
      "-Ymacro-annotations"
    ),
    addCompilerPlugin(
      "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full
    )
  )

还有我的测试

package circuit

import chisel3._
import chiseltest._

import org.scalatest.freespec.AnyFreeSpec
import chisel3.experimental.BundleLiterals._

class IMemorySpec extends AnyFreeSpec with ChiselScalatestTester {
  "memory initial should work by example.hex.txt" in {
    test(new IMemory("src/hex/example.hex.txt")) { dut =>
      dut.io.rdAddr.poke(0.U)
      dut.clock.step()
      dut.io.rdData.expect(0x003100b3.U)
      dut.io.rdAddr.poke(1.U)
      dut.clock.step()
      dut.io.rdData.expect(0x40628033.U)
      dut.io.rdAddr.poke(2.U)
      dut.clock.step()
      dut.io.rdData.expect(0x06432283.U)
      dut.io.rdAddr.poke(3.U)
      dut.clock.step()
      dut.io.rdData.expect(0x06512423.U)
    }
  }
}

它按我的预期工作。

Answer 1

我在 Chisel 6.6.0 中也遇到同样的问题，你解决了吗？