在gem5配置脚本中添加L3缓存时出错

问题描述 投票：0回答：1

我刚刚开始学习gem5，我试图在官方教程中的二级缓存之上添加一个L3缓存。

这些是我根据教程写的L2缓存和L3缓存：

class L2Cache(Cache):
    """Simple L2 Cache with default values"""

    # Default parameters
    size = "256kB"
    assoc = 8
    tag_latency = 20
    data_latency = 20
    response_latency = 20
    mshrs = 20
    tgts_per_mshr = 12

    SimpleOpts.add_option("--l2_size", help=f"L2 cache size. Default: {size}")

    def __init__(self, opts=None):
        super().__init__()
        if not opts or not opts.l2_size:
            return
        self.size = opts.l2_size

    def connectCPUSideBus(self, bus):
        self.cpu_side = bus.mem_side_ports

    def connectMemSideBus(self, bus):
        self.mem_side = bus.cpu_side_ports

class L3Cache(Cache):
    """Simple L3 Cache with default values"""

    # Default parameters
    size = "4MB"
    assoc = 16
    tag_latency = 40
    data_latency = 40
    response_latency = 40
    mshrs = 40
    tgts_per_mshr = 16

    SimpleOpts.add_option("--l3_size", help=f"L3 cache size. Default: {size}")

    def __init__(self, opts=None):
        super().__init__()
        if not opts or not opts.l3_size:
            return
        self.size = opts.l3_size

    def connectCPUSideBus(self, bus):
        self.cpu_side = bus.mem_side_ports

    def connectMemSideBus(self, bus):
        self.mem_side = bus.cpu_side_ports

我假设有两种方法将 L2 缓存连接到 L3 缓存：

  1. 直接将L2端口连接到L3端口。
  2. 在 L2 和 L3 之间声明一条“l3”总线。这辆巴士似乎是
    L2XBar
    ，因为我没有找到任何其他材料。

以下2：

# Create a simple CPU
system.cpu = DerivO3CPU()

# Create an L1 instruction and data cache
system.cpu.icache = L1ICache(args)
system.cpu.dcache = L1DCache(args)

system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)


# Create a memory bus, a coherent crossbar, in this case
system.l2bus = L2XBar()
system.l3bus = L2XBar() # if commented, got abortion errors!!!

# connect
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)

system.l2cache = L2Cache(args)
system.l2cache.connectCPUSideBus(system.l2bus)
system.l3cache = L3Cache(args)

system.membus = SystemXBar()
system.l3cache.connectCPUSideBus(system.l3bus)
system.l2cache.connectMemSideBus(system.l3bus)
system.l3cache.connectMemSideBus(system.membus)

# create the interrupt controller for the CPU
system.cpu.createInterruptController()
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports

# Connect the system up to the membus
system.system_port = system.membus.cpu_side_ports

这会出现以下错误。

src/mem/dram_interface.cc:690: warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
src/base/statistics.hh:279: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
system.remote_gdb: Listening for connections on port 7000
Beginning simulation!
src/sim/simulate.cc:199: info: Entering event queue @ 0.  Starting simulation...
gem5.opt: src/mem/mem_ctrl.cc:701: bool gem5::memory::MemCtrl::addToReadQueue(gem5::PacketPtr, unsigned int, gem5::memory::MemInterface*): Assertion `!readQueueFull(1)' failed.
Program aborted at tick 428000
--- BEGIN LIBC BACKTRACE ---
build/X86/gem5.opt(_ZN4gem515print_backtraceEv+0x30)[0x5625aab171c0]
build/X86/gem5.opt(_ZN4gem512abortHandlerEi+0x4e)[0x5625aab3c39e]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x14420)[0x7f38a9bf3420]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7f38a94ea00b]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x12b)[0x7f38a94c9859]
/lib/x86_64-linux-gnu/libc.so.6(+0x22729)[0x7f38a94c9729]
/lib/x86_64-linux-gnu/libc.so.6(+0x33fd6)[0x7f38a94dafd6]
build/X86/gem5.opt(_ZN4gem56memory7MemCtrl14addToReadQueueEPNS_6PacketEjPNS0_12MemInterfaceE+0xc67)[0x5625aa4393b7]
build/X86/gem5.opt(_ZN4gem56memory7MemCtrl13recvTimingReqEPNS_6PacketE+0x509)[0x5625aa440fd9]
build/X86/gem5.opt(_ZN4gem512CoherentXBar13recvTimingReqEPNS_6PacketEs+0x49c)[0x5625aa411ffc]
build/X86/gem5.opt(_ZN4gem511RequestPort13sendTimingReqEPNS_6PacketE+0x2f)[0x5625aa53432f]
build/X86/gem5.opt(_ZN4gem59BaseCache19sendMSHRQueuePacketEPNS_4MSHRE+0x583)[0x5625aa5311e3]
build/X86/gem5.opt(_ZN4gem55Cache19sendMSHRQueuePacketEPNS_4MSHRE+0x16f)[0x5625aa54b2ef]
build/X86/gem5.opt(_ZN4gem59BaseCache19CacheReqPacketQueue18sendDeferredPacketEv+0xd9)[0x5625aa523629]
build/X86/gem5.opt(_ZN4gem510EventQueue10serviceOneEv+0xc2)[0x5625aab2a0f2]
build/X86/gem5.opt(_ZN4gem59doSimLoopEPNS_10EventQueueE+0x70)[0x5625aab58050]
build/X86/gem5.opt(_ZN4gem58simulateEm+0x29b)[0x5625aab586db]
build/X86/gem5.opt(+0x1dda562)[0x5625ab862562]
build/X86/gem5.opt(+0x8d9c96)[0x5625aa361c96]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x2a8748)[0x7f38a9eaa748]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x8dd8)[0x7f38a9c7ff48]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f38a9dcce4b]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7f38a9eaa124]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f38a9c76d6d]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7f38a9c7eef6]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f38a9dcce4b]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(PyEval_EvalCodeEx+0x42)[0x7f38a9dcd1d2]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(PyEval_EvalCode+0x1f)[0x7f38a9dcd5bf]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x1cfc01)[0x7f38a9dd1c01]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x25f547)[0x7f38a9e61547]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f38a9c76d6d]
/lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x12fd)[0x7f38a9c7846d]
--- END LIBC BACKTRACE ---
For more info on how to address this issue, please visit https://www.gem5.org/documentation/general_docs/common-errors/ 

Aborted (core dumped)

但是，如果遵循 1：

# Create a memory bus, a coherent crossbar, in this case
system.l2bus = L2XBar()
system.l3bus = L2XBar()  # if commented, got abortion errors!!!

# connect
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)

system.l2cache = L2Cache(args)
system.l2cache.connectCPUSideBus(system.l2bus)
system.l3cache = L3Cache(args)

system.membus = SystemXBar()
system.l2cache.mem_side = system.l3cache.cpu_side
system.l3cache.connectMemSideBus(system.membus)

最奇怪的事情发生了。如果我注释掉 

system.l3bus = L2XBar()
，我仍然遇到相同的中止错误（但我已经不再使用 l3bus 了！）。但是，如果我保留这条线，我会得到与这篇文章：

完全相同的输出 
Global frequency set at 1000000000000 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and pdf.
src/mem/dram_interface.cc:690: warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
src/base/statistics.hh:279: warn: One of the stats is a legacy stat. Legacy stat is a stat that does not belong to any statistics::Group. Legacy stat is deprecated.
system.remote_gdb: Listening for connections on port 7000
src/mem/coherent_xbar.cc:140: warn: CoherentXBar system.l3bus has no snooping ports attached!
src/base/statistics.hh:1175: fatal: fatal condition (_x <= 0) || (_y <= 0) occurred: Storage sizes must be positive
Memory Usage: 644212 KBytes

那边的答案没有提供任何帮助。谁能告诉我如何解决这个问题？或者我如何自定义 se.py 脚本，使其具有三级缓存。感谢任何帮助！

caching simulator gem5
1个回答
0
投票

仔细查看错误消息后

gem5.opt: src/mem/mem_ctrl.cc:701: bool gem5::memory::MemCtrl::addToReadQueue(gem5::PacketPtr, unsigned int, gem5::memory::MemInterface*): Assertion `!readQueueFull(1)' failed

我发现这个和读队列、写队列有关系。有关此内容的更多信息，请参见此处。

因此，只需将以下内容添加到配置脚本中，这两种方法都适用于我的原始代码：

system.mem_ctrl.dram.read_buffer_size = 512  # Number of entries in read queue
system.mem_ctrl.dram.write_buffer_size =512  # Number of entries in write queue
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