我的计数器“4位BCD计数器”不能正常工作！
问题描述 投票：0回答：4
我设计了4位BCD计数器和BCD到7段转换器作为我在大学的一门课程的项目。
这是电路：http://img849.imageshack.us/img849/930/111vr.png
这是源代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IC_74163 is
port(LdN, ClrN, P, T, ClK: in std_logic;
D: in std_logic_vector(3 downto 0);
Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
end entity;
architecture IC_74163_1 of IC_74163 is
signal Q: std_logic_vector(3 downto 0); -- Q is the counter register
begin
Qout <= Q;
Cout <= Q(3) and Q(2) and Q(1) and Q(0) and T;
process (CLK)
begin
if CLK'event and CLK = '1' then -- change state on rising edge
if ClrN = '0' then Q <= "0000";
elsif LdN = '0' then Q <= D;
elsif (P and T) = '1' then Q <= Q+1;
end if;
end if;
end process;
end architecture;
================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Four_Digit_BCD_Counter is
port(Clk: in std_logic;
Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
end entity;
architecture Four_Digit_BCD_Counter_1 of Four_Digit_BCD_Counter is
component IC_74163 is
port(LdN, ClrN, P, T, ClK: in std_logic;
D: in std_logic_vector(3 downto 0);
Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
end component;
signal ClrN1, ClrN2, ClrN3, ClrN4: std_logic;
signal T2, T3, T4: std_logic;
begin
ClrN1 <= Q1(3) NOR Q1(0);
ClrN2 <= Q2(3) NOR Q2(0);
ClrN3 <= Q3(3) NOR Q3(0);
ClrN4 <= Q4(3) NOR Q4(0);
T2 <= not (Q1(3) NOR Q1(0));
T3 <= not (Q2(3) NOR Q2(0));
T4 <= not (Q3(3) NOR Q3(0));
IC_1: IC_74163 port map ('1',ClrN1,'1','1',Clk,"ZZZZ",open,Q1);
IC_2: IC_74163 port map ('1',ClrN2,'1',T2,Clk,"ZZZZ",open,Q2);
IC_3: IC_74163 port map ('1',ClrN3,'1',T3,Clk,"ZZZZ",open,Q3);
IC_4: IC_74163 port map ('1',ClrN4,'1',T4,Clk,"ZZZZ",open,Q4);
end architecture;
================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_to_Seven_Segment_Converter is
port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
end entity;
architecture BCD_to_Seven_Segment_Converter_1 of BCD_to_Seven_Segment_Converter is
signal ss:std_logic_vector(6 downto 0);
signal a, b, c, d, e, f, g:std_logic;
begin
a <= B3 or ((not B0) and (not B2)) or B1 or (B0 and B2);
b <= (not B2) or ((not B0) and (not B1)) or (B0 and B1);
c <= (not B1) or B0 or B2;
d <= B3 or ((not B0) and (not B2)) or ((not B0) and B1) or (B0 and (not B1) and B2) or (B1 and (not B2));
e <= ((not B0) and B1) or ((not B0) and (not B2));
f <= B3 or ((not B0) and B2) or ((not B0) and (not B1)) or ((not B1) and B2);
g <= B3 or ((not B1) and B2) or (B1 and (not B2)) or ((not B0) and B1);
process(ss)
begin
case ss is
when "1111110" => output <= 0;
when "0110000" => output <= 1;
when "1101101" => output <= 2;
when "1111001" => output <= 3;
when "0110011" => output <= 4;
when "1011011" => output <= 5;
when "1011111" => output <= 6;
when "1110000" => output <= 7;
when "1111111" => output <= 8;
when "1111011" => output <= 9;
when others => null;
end case;
end process;
--process(input)
--begin
--case input is
--when "0000" => output <= "1111110";
--when "0001" => output <= "0110000";
--when "0010" => output <= "1101101";
--when "0011" => output <= "1111001";
--when "0100" => output <= "0110011";
--when "0101" => output <= "1011011";
--when "0110" => output <= "1011111";
--when "0111" => output <= "1110000";
--when "1000" => output <= "1111111";
--when "1001" => output <= "1111011";
--when others => null;
--end case;
--end process;
end architecture;
================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Project is
port(Clk: in std_logic; Count: out integer range 0000 to 9999 := 0000);
end entity;
architecture The_Circiut of Project is
component Four_Digit_BCD_Counter is
port(Clk: in std_logic;
Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
end component;
component BCD_to_Seven_Segment_Converter is
port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
end component;
signal Qout1, Qout2, Qout3, Qout4: std_logic_vector(3 downto 0):= "0000";
signal D0, D1, D2, D3:integer range 0 to 9;
begin
BCD_Counter_4Digit: Four_Digit_BCD_Counter port map (Clk, Qout1, Qout2, Qout3, Qout4);
BCD_7Segment_Converter1: BCD_to_Seven_Segment_Converter port map (Qout1(0), Qout1(1), Qout1(2), Qout1(3), D0);
BCD_7Segment_Converter2: BCD_to_Seven_Segment_Converter port map (Qout2(0), Qout2(1), Qout2(2), Qout2(3), D1);
BCD_7Segment_Converter3: BCD_to_Seven_Segment_Converter port map (Qout3(0), Qout3(1), Qout3(2), Qout3(3), D2);
BCD_7Segment_Converter4: BCD_to_Seven_Segment_Converter port map (Qout4(0), Qout4(1), Qout4(2), Qout4(3), D3);
Count <= D3 * 1000 + D2 * 100 + D1 * 10 + D0;
end architecture;
问题是，
Count0======================================
编辑：
好吧，在我编辑了@MRAB和@Tomi Junnila提到的问题后，问题并没有解决！ 另外，我尝试单独测试
IC_74163QoutX======================================
编辑2：
这是
IC_74163
======================================
编辑3：
好的，计数器工作得很好，但我仍然有一个很小的问题。我有四个
std_logic_vector(3 downto 0)Qout1Qout2Qout3Qout4std_logic_vector(3 downto 0):= "0000"======================================
编辑4：
好的，伙计们，计数器正在按要求工作，没有任何问题。谢谢您的帮助，我真的很感激。
以下是感兴趣的人的最终源代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IC_74163 is
port(LdN, ClrN, P, T, ClK: in std_logic:='0';
D: in std_logic_vector(3 downto 0):="0000";
Cout: out std_logic; Qout: inout std_logic_vector(3 downto 0):="0000");
end entity;
architecture IC_74163_1 of IC_74163 is
begin
Cout <= Qout(3) and Qout(2) and Qout(1) and Qout(0) and T;
process (CLK)
begin
if CLK'event and CLK = '1' then -- change state on rising edge
if ClrN = '0' then Qout <= "0000";
elsif LdN = '0' then Qout <= D;
elsif (P and T) = '1' then Qout <= Qout+1;
end if;
end if;
end process;
end architecture;
================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Four_Digit_BCD_Counter is
port(Clk: in std_logic;
Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
end entity;
architecture Four_Digit_BCD_Counter_1 of Four_Digit_BCD_Counter is
component IC_74163 is
port(LdN, ClrN, P, T, ClK: in std_logic;
D: in std_logic_vector(3 downto 0);
Cout: out std_logic; Qout: inout std_logic_vector(3 downto 0) );
end component;
signal ClrN1, ClrN2, ClrN3, ClrN4: std_logic;
signal T2, T3, T4: std_logic;
begin
ClrN1 <= Q1(3) NAND Q1(0);
ClrN2 <= Q2(3) NAND Q2(0);
ClrN3 <= Q3(3) NAND Q3(0);
ClrN4 <= Q4(3) NAND Q4(0);
T2 <= not (Q1(3) NAND Q1(0));
T3 <= not (Q2(3) NAND Q2(0));
T4 <= not (Q3(3) NAND Q3(0));
IC_1: IC_74163 port map ('1',ClrN1,'1','1',Clk,"ZZZZ",open,Q1);
IC_2: IC_74163 port map ('1',ClrN2,'1',T2,Clk,"ZZZZ",open,Q2);
IC_3: IC_74163 port map ('1',ClrN3,'1',T3,Clk,"ZZZZ",open,Q3);
IC_4: IC_74163 port map ('1',ClrN4,'1',T4,Clk,"ZZZZ",open,Q4);
end architecture;
================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_to_Seven_Segment_Converter is
port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
end entity;
architecture BCD_to_Seven_Segment_Converter_1 of BCD_to_Seven_Segment_Converter is
signal ss:std_logic_vector(6 downto 0);
signal a, b, c, d, e, f, g:std_logic;
begin
a <= B3 or ((not B0) and (not B2)) or B1 or (B0 and B2);
b <= (not B2) or ((not B0) and (not B1)) or (B0 and B1);
c <= (not B1) or B0 or B2;
d <= B3 or ((not B0) and (not B2)) or ((not B0) and B1) or (B0 and (not B1) and B2) or (B1 and (not B2));
e <= ((not B0) and B1) or ((not B0) and (not B2));
f <= B3 or ((not B0) and B2) or ((not B0) and (not B1)) or ((not B1) and B2);
g <= B3 or ((not B1) and B2) or (B1 and (not B2)) or ((not B0) and B1);
ss <= a&b&c&d&e&f&g;
process(ss)
begin
case ss is
when "1111110" => output <= 0;
when "0110000" => output <= 1;
when "1101101" => output <= 2;
when "1111001" => output <= 3;
when "0110011" => output <= 4;
when "1011011" => output <= 5;
when "1011111" => output <= 6;
when "1110000" => output <= 7;
when "1111111" => output <= 8;
when "1111011" => output <= 9;
when others => null;
end case;
end process;
--process(input)
--begin
--case input is
--when "0000" => output <= "1111110";
--when "0001" => output <= "0110000";
--when "0010" => output <= "1101101";
--when "0011" => output <= "1111001";
--when "0100" => output <= "0110011";
--when "0101" => output <= "1011011";
--when "0110" => output <= "1011111";
--when "0111" => output <= "1110000";
--when "1000" => output <= "1111111";
--when "1001" => output <= "1111011";
--when others => null;
--end case;
--end process;
end architecture;
================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Project is
port(Clk: in std_logic; Count: out integer range 0000 to 9999 := 0000);
end entity;
architecture The_Circiut of Project is
component Four_Digit_BCD_Counter is
port(Clk: in std_logic;
Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
end component;
component BCD_to_Seven_Segment_Converter is
port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
end component;
signal Qout1, Qout2, Qout3, Qout4: std_logic_vector(3 downto 0):= "0000";
signal D0, D1, D2, D3:integer range 0 to 9;
begin
BCD_Counter_4Digit: Four_Digit_BCD_Counter port map (Clk, Qout1, Qout2, Qout3, Qout4);
BCD_7Segment_Converter1: BCD_to_Seven_Segment_Converter port map (Qout1(3), Qout1(2), Qout1(1), Qout1(0), D0);
BCD_7Segment_Converter2: BCD_to_Seven_Segment_Converter port map (Qout2(3), Qout2(2), Qout2(1), Qout2(0), D1);
BCD_7Segment_Converter3: BCD_to_Seven_Segment_Converter port map (Qout3(3), Qout3(2), Qout3(1), Qout3(0), D2);
BCD_7Segment_Converter4: BCD_to_Seven_Segment_Converter port map (Qout4(3), Qout4(2), Qout4(1), Qout4(0), D3);
Count <= D3 * 1000 + D2 * 100 + D1 * 10 + D0;
end architecture;
4个回答
3
投票
投票
您没有为
ssBCD_to_Seven_Segment_Converter_1outputag还有一种更简单的方法将 4 位转换为整数：
--...
signal v : std_logic_vector(3 downto 0);
begin
v <= B3 & B2 & B1 & B0;
CONV: process(v)
case v is
when "0000" => output <= 0;
when "0001" => output <= 1;
when "0010" => output <= 2;
-- etc, don't forget "when others"
end case;
end process CONV;
--...
您可能也没有正确重置
IC_74163ClrNClrNQout2
投票
投票
我已经很久没有看过这样的东西了，但我认为问题可能是你说的是NOR而不是NAND，所以应该是，例如：
ClrN1 <= Q1(3) NAND Q1(0);
1
投票
投票
你的问题不是“计数永远保持0并且不会改变和计数”。 您的问题是 Count 未定义，并且向未定义的值加一也是未定义的。
您需要提供上电复位或以其他方式将 Q() 值初始化为已知状态，然后您应该会看到您期望的行为。 有很多方法可以做到这一点，但也许最简单的（对现有代码的改动最少）是在声明 Q 信号时提供一个初始值：
architecture IC_74163_1 of IC_74163 is
signal Q: std_logic_vector(3 downto 0) := "0000" ; -- Q is the counter register
0
投票
投票
模块顶部_模块（ 输入时钟， 输入复位，//同步高电平有效复位 输出 reg [3:1] ena, 输出寄存器[15:0]q );
always @(posedge clk) begin
if(reset) begin
q = 0;
ena = 0;
end
else begin
q[3:0] = q[3:0] + 1;
if(q[3:0] == 9) begin
ena[1] = 1;
end
else begin
ena[1] = 0;
end
if(q[3:0] == 10) begin
q[3:0] = 0;
q[7:4] = q[7:4] + 1;
end
if((q[7:4] == 9) && (q[3:0] == 9)) begin
ena[2] = 1;
end
else begin
ena[2] = 0;
end
if(q[7:4] == 10) begin
q[7:4] = 0;
q[11:8] = q[11:8] + 1;
end
if((q[11:8] == 9) && (q[7:4] == 9) && (q[3:0] == 9)) begin
ena[3] = 1;
end
else begin
ena[3] = 0;
end
if(q[11:8] == 10) begin
q[11:8] = 0;
q[15:12] = q[15:12] + 1;
end
if(q[15:12] == 10) begin
q = 0;
end
end
end
结束模块 //它可能对你有帮助
最新问题
- 使用应用程序脚本在 Google Drive 内的 Excel 中提取数据
- 这个回溯问题是怎么回事？
- 如何让 .pdf 文档的标题显示为页面标题？
- HttpErrorResponse仅出现在角度终端输出中，但应用程序中没有错误
- Firefox 插件：如何将当前网址发送到后台脚本
- .NET Core：使用多个 HttpClientFactory 实例的效率
- 根据值从表中返回特定列的函数
- Node + Neo4j 驱动程序 - 有没有办法设置“全局”类型转换器，以便任何日期时间属性都是 ISO8601 字符串而不是 JS 对象？
- 如何使用 python gmail API（有效）将超链接插入现有电子邮件（通过插入/删除 API 函数）而不被破坏？
- 更改显示器图像的宽度时：弯曲一切都会中断
- 将复杂的 python 类序列化为 JSON
- 错误：不支持通过“next.config.ts”配置 Next.js。请将文件替换为“next.config.js”
- 使用 BeautifulSoup 当有工作可用时提醒我
- 如何处理 CI/CD 管道中的 CloudFormation 更新限制？
- 使用 ODBC 将 powerBI Desktop 连接到 AWS Athena 错误
- 在Android上，您必须使用WithParentActivityOrWindow方法指定将显示浏览器弹出窗口的当前Activity
- x86 AT&T 语法汇编的注释语法
- 作为电报机器人，验证电报频道所有者的最佳方法是什么？
- Laravel 11 OpenAdmin 在创建控制器时给出错误方法 Illuminate\Database\MySqlConnection::isDoctrineAvailable 不存在
- 带有打包项目的uwp的多个msixupload文件
© www.soinside.com 2019 - 2024. All rights reserved.