Verilog BRAM 排序

Question

我想在verilog中推断8x4单端口BRAM，我必须读取RAM的值并对它们进行排序。在排序过程中，我需要通过写入最低内存地址来对RAM数据从最小到最大进行排序。但是我在 verilog 中遇到了一些错误，但我无法理解它们。这是我的 Verilog BRAM 代码。

`timescale 1ns / 1ps

module DS(
 input clk, // clock signal
 input [2:0] ram_addr, // RAM address input
 input [3:0] ram_data_in, // RAM data input
 output reg [3:0] ram_data_out, // RAM data output
 input ram_we // RAM write enable
    );

// Declare RAM array
reg [3:0] ram [0:7];

// Define RAM behavior
always @(posedge clk) begin
    if (ram_we) begin
        ram[ram_addr] <= ram_data_in; // write to RAM
    end
    ram_data_out <= ram[ram_addr]; // read from RAM
end   
    
endmodule

这是我的sorting_mem（排序过程）模块

`timescale 1ns / 1ps

module Sort_mem(
 input clk, // clock signal
 output reg [3:0] min, // minimum value
 output reg [2:0] min_addr, // minimum value address
 output [3:0] ram_out, // RAM output
 input [3:0] ram_in, // RAM output
 input [2:0] ram_addr,
 input ram_we 
    );
// Declare RAM signals

reg [3:0] ram_data_in; // RAM data input
reg [3:0] out; // RAM data output
reg write; // RAM write enable
reg [2:0] ADRES;
// Instantiate RAM module
DS ds_inst(
    .clk(clk),
    .ram_addr(ADRES),
    .ram_data_in(ram_data_in),
    .ram_data_out(out),
    .ram_we(write)
);

// Define sort logic
reg [3:0] counter; // loop counter
always @(posedge clk) begin
    // Initialize min, min_addr and counter
    min <= ram_data_out;
    min_addr <= 0;
    counter <= 0;
    // Use case statement to loop through RAM elements
    case (counter)
        0: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 0;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        1: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 1;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        2: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 2;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        3: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 3;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        4: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 4;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        5: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 5;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        6: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 6;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        7: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 7;
            end
            // Write min to lowest RAM address
            write <= 1;
            ram_data_in <= min;
            ADRES <= 0;
            // Reset counter and write enable
            counter <= 0;
            write <= 0;
        end
    endcase
end
assign ram_in = ram_data_in;
assign ram_out = ram_data_out;

endmodule

这是测试台

`timescale 1ns / 1ps

module test();
reg clk;
reg yaz;
reg adres;
reg data;
reg out;

Sort_mem uut(.clk(clk),.ram_we(yaz),.ram_addr(adres), .ram_in(data), .ram_out(OUT));
always
begin
    #5
    clk <= ~clk;
end
initial
begin
    clk <= 0;   
    yaz <= 0;
    adres <= 0;
    data <= 0;

    #10

    yaz <= 1;
    adres <= 7;
    data <= 7;
   
    #10
    adres <= 6;
    data <= 4;
   
    #10
    adres <= 5;
    data <= 9;

    #10
    adres <= 4;
    data <= 3;
    #10
    adres <= 3;
    data <= 3;
     #10
    adres <= 2;
    data <= 3;
    
     #10
    adres <= 1;
    data <= 3;
     #10
    adres <= 0;
    data <= 3;
    #10
    yaz <= 0;
    #40
    $finish;
end
endmodule

这里是错误

[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Vivado Project/BRAM_DENEME/BRAM_DENEME.sim/sim_1/behav/xsim/xvlog.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

我的verilog代码中的可见错误就在这个“`timescale 1ns / 1ps”上，它是“错误：刷新期间解析信息不可用” 我必须在不使用 for 循环的情况下执行排序过程。

我尝试将 ram_out reg 转换为wire。我希望看到模拟屏幕和排序值，但我看不到

Answer 1

您的模拟器没有给您非常有用的错误消息。

您可以在 EDA Playground 上的其他模拟器上编译代码，以获得更多有用的消息。

在Sort_mem模块中更改：

 output [3:0] ram_out, // RAM output

至：

 output [3:0] ram_data_out, // RAM output

并删除这一行：

assign ram_out = ram_data_out;

然后，在测试模块中，更改：

Sort_mem uut(.clk(clk),.ram_we(yaz),.ram_addr(adres), .ram_in(data), .ram_out(OUT));

至：

Sort_mem uut(.clk(clk),.ram_we(yaz),.ram_addr(adres), .ram_in(data), .ram_data_out(OUT));

这修复了编译错误。但是，您仍然会看到应该修复的编译警告。