在 TCL 中解析输入文件时提取错误的值

问题描述 投票：0回答：1

我有一个格式为的输入文件

https://regex101.com/r/4VAKoQ/1

我编写了TCL代码来从Other End Path部分提取一些值，以便它应该以以下格式输出

记住输入文本文件可能有数百个这样的路径

results_c.txt 中的预期输出

PathID STA spice diff %diff

Path1 816.500 829.700 -13.2  1.603%
Path2 816.500 829.700 -13.2   1.603%

但是，使用我当前的代码，我得到的输出低于

PathID STA spice diff %diff

Path1 9.619 12.300 -2.681000000000001 21.796747967479682%
Path2 9.619 12.300 -2.681000000000001 21.796747967479682%

仅注意在这种情况下，Path1 和 Path2 值匹配是巧合

这是我的 TCL 代码，我的正则表达式必须修改和更正。

#!/usr/bin/env tclsh

# Open the input file and create an output file set input [open "/mnt/data/inputs.txt" r] set output [open "/mnt/data/results_c.txt" w] puts $output "PathID STA spice diff %diff"

# Initialize variables set current_path "" set capture 0 array set data {}

# Read the file line by line while {[gets $input line] != -1} {
    # Check for the start of a new path
    if {[regexp {PathID: (\d+)} $line match path_id]} {
        set current_path $path_id
        set capture 0
    }

    # Detect the "Other End Path" section
    if {$current_path ne "" && [string match "*Other End Path:*" $line]} {
        set capture 1
        continue
    }

    # Capture the last line of current path's "Other End Path" section
    if {$capture == 1 && [regexp {(\d+\.\d+)\s+(\d+\.\d+)} $line -> sta spice]} {
        set data($current_path) [list $sta $spice]
    } }

# Process captured data foreach path [array names data] {
    set values $data($path)
    set sta [lindex $values 0]
    set spice [lindex $values 1]
    set diff [expr {$sta - $spice}]
    set percent_diff [expr {abs($diff / $spice) * 100}]
    puts $output "Path$path $sta $spice $diff $percent_diff%" }

# Close files close $input close $output

puts "Data has been processed and results are written to /mnt/data/results_c.txt"

输入

PathID: 1
###############################################################
#  S
#  O
#  M
#  E
TEXT
###############################################################
Path 1: 
 SOME TEXT
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#   Load   Trans   Trans   Trans    Delay    Spice   Delay   Arrival     Spice          Duty Cycle                      Toggle  Edge  Condition           Cell               Pin  
#   (ff)  Retime   Spice   Error   Retime    Delay   Error      (ps)   Arrival                                            Rate                                                 
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  21.050   3.100   3.100   0.000        -        -       -     0.000         -  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -                   (arrival)          CLK  
  21.050  17.400  18.200  -0.800   11.700   11.800  -0.100    11.700    11.800  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -                   AA0SScbf000ha1n24x5 
Xtensa_LoadStore/ls_low_low_to_high_993_UPF_LS/o  
  <some more lines> 
   0.464   4.400   4.500  -0.100    0.000    0.100  -0.100   731.100   774.200  { 0.062 : 0.062 }   { 3.237e+09 : 3.237e+09 }   F     -                   AA0SSfvn003aa1d12x5  Xtensa_PCandIFetch_PCUnit_killPipe_W_reg_tmp_reg[0]/d  
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
     Other End Path:

#-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#   Load   Trans   Trans   Trans    Delay    Spice   Delay   Arrival     Spice          Duty Cycle                      Toggle  Edge  Condition       Cell               Pin  
#   (ff)  Retime   Spice   Error   Retime    Delay   Error      (ps)   Arrival                                            Rate                                             
#-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  20.663   3.100   3.100   0.000        -        -       -   714.000         -  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -               (arrival)          CLK  
  20.663  17.400  18.200  -0.800   11.700   11.800  -0.100   725.700   725.800  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -               AA0SScbf000ha1n24x5  CTS_cdb_buf_00544/clk  
<some repeating lines of data>
9.619  12.300  14.600  -2.300    3.200    3.300  -0.100   816.500   829.700  { 0.050 : 0.050 }   { 1.900e+09 : 1.900e+09 }   R     -               AA0SSfvn003aa1d12x5  Xtensa_PCandIFetch_PCUnit_killPipe_W_reg_tmp_reg[0]/clk  
#-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

PathID: 2
###############################################################
#  S
#  O
#  M
#  E
TEXT
###############################################################
Path 1: 
 SOME TEXT withfew lines
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#   Load   Trans   Trans   Trans    Delay    Spice   Delay   Arrival     Spice          Duty Cycle                      Toggle  Edge  Condition           Cell               Pin  
#   (ff)  Retime   Spice   Error   Retime    Delay   Error      (ps)   Arrival                                            Rate                                                 
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
21.050   3.100   3.100   0.000        -        -       -     0.000         -  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -                   (arrival)          CLK  
  21.050  17.400  18.200  -0.800   11.700   11.800  -0.100    11.700    11.800  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -                   AA0SScbf000ha1n24x5  CTS_cdb_buf_00544/clk  
   <some repeating lines with different values in same format> 
   0.464   4.400   4.500  -0.100    0.000    0.100  -0.100   731.100   774.200  { 0.062 : 0.062 }   { 3.237e+09 : 3.237e+09 }   F     -                   AA0SSfvn003aa1d12x5  Xtensa_PCandIFetch_PCUnit_killPipe_W_reg_tmp_reg[0]/d  
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
     Other End Path:

#-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#   Load   Trans   Trans   Trans    Delay    Spice   Delay   Arrival     Spice          Duty Cycle                      Toggle  Edge  Condition       Cell               Pin  
#   (ff)  Retime   Spice   Error   Retime    Delay   Error      (ps)   Arrival                                            Rate                                             
#-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  20.663   3.100   3.100   0.000        -        -       -   714.000         -  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -               (arrival)          CLK  
  20.663  17.400  18.200  -0.800   11.700   11.800  -0.100   725.700   725.800  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -               AA0SScbf000ha1n24x5  CTS_cdb_buf_00544/clk  
9.619  10.300  12.700  -2.400   14.500   17.300  -2.800   813.300   826.400  { 0.050 : 0.050 }   { 1.900e+09 : 1.900e+09 }   R     -               AA0SScbf000aa1n24x5  CTS_cdb_buf_00584/clkout  
   9.619  12.300  14.600  -2.300    3.200    3.300  -0.100   816.500   829.700  { 0.050 : 0.050 }   { 1.900e+09 : 1.900e+09 }   R     -               AA0SSfvn003aa1d12x5  Xtensa_PCandIFetch_PCUnit_killPipe_W_reg_tmp_reg[0]/clk  
#-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
arrays regex sorting parsing tcl
1个回答
0
投票

您可以利用 

{
和 
Xtensa_
来编写您的模式：

例如，您可以使用如下模式：

set pattern {([-+]?\d+\.\d+)\s+([-+]?\d+\.\d+)\s+\{\s+.*Xtensa_}
:

set text {21.050   3.100   3.100   0.000        -        -       -     0.000         -  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -                   (arrival)          CLK
21.050  17.400  18.200  -0.800   11.700   11.800  -0.100    11.700    11.800  { 0.600 : 0.600 }   { 1.900e+09 : 1.900e+09 }   R     -                   AA0SScbf000ha1n24x5  CTS_cdb_buf_00544/clk
0.464   4.400   4.500  -0.100    0.000    0.100  -0.100   731.100   774.200  { 0.062 : 0.062 }   { 3.237e+09 : 3.237e+09 }   F     -                   AA0SSfvn003aa1d12x5  Xtensa_PCandIFetch_PCUnit_killPipe_W_reg_tmp_reg[0]/d}


set pattern {([-+]?\d+\.\d+)\s+([-+]?\d+\.\d+)\s+\{\s+.*Xtensa_}


foreach line [split $text "\n"] {
    if {[regexp $pattern $line -> num1 num2]} {
        puts "$num1 $num2"
    }
}

打印

731.100 774.200
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