VHDL 浮点加法器/减法器 - 边界检查错误

Question

我正在为浮点加法器/减法器编写代码。我有多个错误，所以我正在调试，此时，当尝试模拟时，我在代码下方收到错误：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fp_sum_subs is
    generic (
        NE: natural := 8;
        NF: natural := 23
    );
    port (
        rst:      in std_logic;
        clk:      in std_logic;
        sum_subs: in std_logic;
        x:   in std_logic_vector(NF+NE downto 0);
        y:   in std_logic_vector(NF+NE downto 0);
        z:   out std_logic_vector(NF+NE downto 0);

        mx_p :   out unsigned(NF downto 0);
        my_p :   out unsigned(NF downto 0);

        sx :             out std_logic;
        fx :             out std_logic_vector(NF-1 downto 0);
        ex :             out unsigned(NE-1 downto 0);

        sy :             out std_logic;
        fy :             out std_logic_vector(NF-1 downto 0);
        ey :             out unsigned(NE-1 downto 0);

        mx:              out unsigned(NF downto 0);
        my:              out unsigned(NF downto 0)
    );
end fp_sum_subs;

architecture behavioral of fp_sum_subs is
    constant EXC : signed(NE+1 downto 0) := to_signed((2**(NE-1)) - 1, NE+2);
    signal x_reg :          std_logic_vector(NF+NE downto 0);
    signal y_reg :          std_logic_vector(NF+NE downto 0);
    signal sum_subs_reg:    std_logic;
    -- signal sx :             std_logic;
    -- signal fx :             std_logic_vector(NF-1 downto 0);
    -- signal ex :             unsigned(NE-1 downto 0);
    signal ex_ext :         signed(NE downto 0);
    -- signal sy :             std_logic;
    -- signal fy :             std_logic_vector(NF-1 downto 0);
    -- signal ey :             unsigned(NE-1 downto 0);
    signal ey_ext :         signed(NE downto 0);
    signal exp_diff:        signed(NE downto 0);
    signal abs_exp_diff :   unsigned(NE downto 0);
    -- signal mx :             unsigned(NF downto 0);
    -- signal my :             unsigned(NF downto 0);
    signal mx_p_nt_a:       signed(2**NE downto 0);
    signal my_p_t_a:        signed(2**NE downto 0);

    -- signal mx_p :             unsigned(NF downto 0);
    -- signal my_p :             unsigned(NF downto 0);

begin

    process(clk, rst)
    begin
        if rst = '1' then
            x_reg <= (others => '0');
            y_reg <= (others => '0');
            sum_subs_reg <= '0';
        elsif rising_edge(clk) then
            x_reg <= x;
            y_reg <= y;
            sum_subs_reg <= sum_subs;
        end if;
    end process;

    sx <= x_reg(NF+NE);
    fx <= x_reg(NF-1 downto 0);
    ex <= unsigned(x_reg(NF+NE-1 downto NF));

    sy <= y_reg(NF+NE);
    fy <= y_reg(NF-1 downto 0);
    ey <= unsigned(y_reg(NF+NE-1 downto NF));

    ex_ext <= signed('0' & std_logic_vector(ex));
    ey_ext <= signed('0' & std_logic_vector(ey));

    exp_diff <= ex_ext - ey_ext;

    process(all) begin
        if exp_diff(NE) = '1' then
            abs_exp_diff <= unsigned(not(std_logic_vector(exp_diff))) + 1;
        else
            abs_exp_diff <= unsigned(exp_diff);
        end if;
    end process;

    mx <= unsigned('1' & fx);
    my <= unsigned('1' & fy);

    mx_p <= mx when exp_diff(NE) = '0' else my;

    my_p <= my when exp_diff(NE) = '0' else mx;

    -- -- TODO bound check error
    mx_p_nt_a   <=      signed(
                         std_logic_vector(to_unsigned(0, 2**NE - 1 - NF - abs_exp_diff)) &
                         std_logic_vector(mx_p)                                          &
                         std_logic_vector(to_unsigned(0, abs_exp_diff))
                         );
     my_p_t_a    <=      signed(
                         std_logic_vector(to_unsigned(0, 2**NE - 1 - NF))                &
                         std_logic_vector(my_p)
                         );

end architecture behavioral;

 

这是错误，我不明白出了什么问题。

$ make
ghdl -a --std=08 ../../rtl/fp_sum_subs.vhd
ghdl -a --std=08 ../../tb/tb.vhd
ghdl -e --std=08 tb
ghdl -r --std=08 tb --wave=waves.ghw
ghdl:error: bound check failure at ../../rtl/fp_sum_subs.vhd:101
ghdl:error: simulation failed
make: *** [Makefile:35: tb.out] Error 1

我尝试更改 mx_p_nt_a my_p_t_a 的大小，并添加一位和少一位，但我仍然遇到相同的错误。

Answer 1

以 unsigned 作为第二个参数（名为 SIZE_RES）的函数 to_unsigned 定义为：

  function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED)
      return UNRESOLVED_UNSIGNED is
  begin
      return TO_UNSIGNED (ARG  => ARG,
                          SIZE => SIZE_RES'length);
  end function TO_UNSIGNED;

返回值是一个无符号的值，其长度为第二个参数SIZE_RES。

您的第二个参数是“2**NE - 1 -NF - abs_exp_diff”。 因此该函数不使用由该表达式计算的值， 但它的长度，由abs_exp_diff的长度决定。 因此，串联的第一个表达式给出 NE+1 位。

第二个有 NF+1 位。

第三个又是 NE+1 位（abs_exp_diff 的长度）。

但是 mx_p_nt_a 有 2*NE+1 位，与 NE+1+NF+1+NE+1 不同。