verilog HDL 时钟

Question

设计一个显示分、秒的定时器电路 HEX3、HEX2、HEX1、HEX0由DE10 FPGA板上的KEYS控制，使用Verilog HDL语言。

在那里：

• KEY0 用于将时钟重置为“00:00”
• KEY1 用于开始或暂停计时（时钟继续 再次按下 KEY1 时计数）

要求与建议：

• 使用计数器并比较以创建精确的 1Hz 时钟 来自50MHz时钟（创造最精确的1秒实时）；柜台 可以单独设计成单独的模块并调用到设计中 （实例化）
• HEX 显示解码功能被设计为单独的模块

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Answer 1

打开电源时时钟不开始计数，只有按住按钮时才停止 // 用于从 50MHz 时钟生成 1Hz 时钟的模块 clk_divider( input clk_50M, // 50MHz 时钟输入 input rst, / /复位输入输出reg clk_1Hz //1Hz时钟输出); 参数N = 25_000_000； // 除法的周期数 reg [24:0] counter; // 25位计数器 总是 @(posege clk_50M 或 posege rst) 开始 if (rst) 开始 柜台<= 0; clk_1Hz <= 0; end else begin if (counter == N-1) begin counter <= 0; clk_1Hz <= ~clk_1Hz; // toggle the output end else begin counter <= counter + 1; end end end endmodule // Module for decoding and displaying digits on HEX module hex_decoder( input [3:0] digit, // 4-bit digit input output reg [6:0] hex // 7-bit hex output ); always @(*) begin case (digit) 4'h0: hex = 7'b1000000; // display 0 4'h1: hex = 7'b1111001; // display 1 4'h2: hex = 7'b0100100; // display 2 4'h3: hex = 7'b0110000; // display 3 4'h4: hex = 7'b0011001; // display 4 4'h5: hex = 7'b0010010; // display 5 4'h6: hex = 7'b0000010; // display 6 4'h7: hex = 7'b1111000; // display 7 4'h8: hex = 7'b0000000; // display 8 4'h9: hex = 7'b0010000; // display 9 default: hex = 7'b1111111; // display nothing endcase end endmodule // Module for designing the timer circuit module test1( input clk_50M, // 50MHz clock input input rst, // reset input input start_stop, // start/stop input output [6:0] hex0, // hex0 output output [6:0] hex1, // hex1 output output [6:0] hex2, // hex2 output output [6:0] hex3 // hex3 output ); wire clk_1Hz; // 1Hz clock wire reg run; // run flag register reg [3:0] second_low; // lower digit of second register reg [3:0] second_high; // higher digit of second register reg [3:0] minute_low; // lower digit of minute register reg [3:0] minute_high; // higher digit of minute register // Instantiate the clk_divider module clk_divider clk_div( .clk_50M(clk_50M), .rst(rst), .clk_1Hz(clk_1Hz) ); // Instantiate the hex_decoder module four times hex_decoder hex_dec0( .digit(second_low), .hex(hex0) ); hex_decoder hex_dec1( .digit(second_high), .hex(hex1) ); hex_decoder hex_dec2( .digit(minute_low), .hex(hex2) ); hex_decoder hex_dec3( .digit(minute_high), .hex(hex3) ); // Logic for controlling the run flag always @(posedge clk_1Hz or posedge rst) begin if (rst) begin run <= 0; end else begin if (start_stop) begin run <= ~run; // toggle the run flag end end end // Logic for counting the time always @(posedge clk_1Hz or posedge rst) begin if (rst) begin second_low <= 0; second_high <= 0; minute_low <= 0; minute_high <= 0; end else begin if (run) begin if (second_low == 4'h9) begin second_low <= 0; if (second_high == 4'h5) begin second_high <= 0; if (minute_low == 4'h9) begin minute_low <= 0; if (minute_high == 4'h5) begin minute_high <= 0; end else begin minute_high <= minute_high + 1; end end else begin minute_low <= minute_low + 1; end end else begin second_high <= second_high + 1; end end else begin second_low <= second_low + 1; end end end end endmodule