第49行：综合时不支持多个单边下的赋值

Question

我尝试更改各种不同的问题，例如

begin-end

声明，但似乎没有任何效果。我还尝试将

reg [3:0]

更改为

[7:0]

，因为我也收到了一些警告

我不确定为什么我不断收到此错误：

#  Line 49: Assignment under multiple single edges is not supported for synthesis

`timescale 1ns / 1ps
module FSM (CLK, U, D, CL, Z);  
     
 input CLK, U, D, CL; 
 reg [3:0] count;
 output reg [3:0] Z;
 
 always @ (posedge CLK or posedge CL) begin
    if(CL)
        count <= 0;
    else
            begin
        if(U)
        begin
            if(count == 8)
            count <= 0;
                else
            count <= count +1;
            end
            if(D)
            begin
            if(count == 0)
                count <= 8;
            else
                count <= count -1;
            end
        end
        
if(count==0)
    Z<=8;
if(count==1)
    Z<=2;
if(count==2)
    Z<=6;
if(count==3)
    Z<=4;
if(count==4)
    Z<=6;
if(count==5)
    Z<=8;
if(count==6)
    Z<=0;
if(count==7)
    Z<=7;
if(count==8)
    Z<=8;
end
endmodule

Answer 1

综合工具可能会感到困惑，因为

Z

不像

CL

那样由

count

信号异步重置。

我认为最好重置

Z

并将代码分成2个

always

块：

module FSM (CLK, U, D, CL, Z);  
   
    input CLK, U, D, CL; 
    reg [3:0] count;
    output reg [3:0] Z;
   
    always @ (posedge CLK or posedge CL) begin
        if (CL)
            count <= 0;
        else begin
           if (U) begin
                if (count == 8)
                    count <= 0;
                else
                    count <= count + 1;
            end
            if (D) begin
                if (count == 0)
                    count <= 8;
                else
                    count <= count - 1;
            end
        end
    end

    always @ (posedge CLK or posedge CL) begin
        if (CL) begin
            Z <= 0;
        end else begin
            case (count)
                0: Z <= 8;
                1: Z <= 2;
                2: Z <= 6;
                3: Z <= 4;
                4: Z <= 6;
                5: Z <= 8;
                6: Z <= 0;
                7: Z <= 7;
                8: Z <= 8;
            endcase
        end
    end

endmodule

请注意，我还对

case

使用了

Z

语句来简化代码并使意图更加明显。