Xilinx Vivado 2023 IP 模块设计问题：无法将 RTL 模块的输出连接到连接到 LED 的 AXI GPIO 输出

Question

我使用的是 Vivado 2023.1，并且无法将 RTL 模块的输出连接到连接到 LED 的 AXI GPIO 输出。请看一下附件。 RTL 如下

module led_blinker (
    input wire sysclk,
    input wire rst,
    output reg led
);

    reg [26:0] counter;
    reg led_state;

    

//TO make reset signal work with PS, make sure it is negedge reset
    always @(posedge sysclk or negedge rst) begin
        if (~rst) begin
            counter <= 27'd0;
            led_state <= 1'b0;
        end else begin
            if (counter == 27'd99999999) begin  // Adjust for desired blink rate
                counter <= 27'd0;
                led_state <= ~led_state;
            end else begin
                counter <= counter + 1'b1;
            end
        end
    end

        always @(*)
     begin
        led = led_state;
    end

endmodule

Answer 1

您无法将两个输出连接在一起。它必须从输出到输入。