流水线架构中 Verilog 中的信号传播问题

问题描述 投票：0回答：1

我正在研究一种混合排序流水线架构，它结合了双调排序和双向插入排序。我已经实现了双调排序（BSU）单元和双向插入排序（BISU）单元。 BISU 具有序列重排逻辑 (SRL) 和双向插入排序逻辑 (BISL)。下面的代码应该对 8 个数据的序列进行排序。 8 个数据序列被分为 2 个 4 个子序列。该架构一次输入 4 个数据。对于 N 个数据，需要 N/2 个 BISU 单元。该架构有一个 4 输入 BSU 单元，并连接到 4 个 BISU 单元。首先使用双调排序对 4 个数据进行预排序，然后发送到 BISU 单元，在其中对输入序列进行排序。

当我单独测试每个块时，我得到缩进输出，但是当我将它们连接在一起时，BSU 单元的输出会传播到第一个 BISU 单元，但第一个 BISU 单元的输出不会传播到第二个 BISU 单元等等。有人可以告诉我我做错了什么吗？

我已经给出了我在下面实现的代码及其模拟和测试平台。 DI 代表数据输入，DO 代表数据输出。

This is the simulation for the module BSU_BISU_8_4

预期输出：

循环 0 1 2 3 4 5 6 7 8
CN 1 1 1 1 1 1 1 1 1
INV 0 0 0 0 0 0 0 0 0
RST 1 0 0 0 0 0 0 0 0
DO1 - 2 8 0 15 x x x x
DO2 - 13 10 0 15 x x x x
DO3 - 1 15 0 15 x x x x
DO4 - 5 1 0 15 x x x x
DO1 x x x x x 15 15 1 8
DO2 x x x x x 15 15 1 10
DO3 x x x x x 0 0 2 13
DO4 x x x x x 0 0 5 15
a1 x 1 1 0 15 x x x x
a2 x 2 8 0 15 x x x x
a3 x 5 10 0 15 x x x x
a4 x 13 15 0 15 x x x x
b1 x x 2 1 0 15 x x x
b2 x x 15 8 0 15 x x x
b3 x x 0 10 0 15 x x x
b4 x x 5 13 1 15 x x x
c1 x x x 15 2 0 13 x x
c2 x x x 15 5 0 15 x x
c3 x x x 0 8 1 15 x x
c4 x x x 0 10 1 15 x x
d1 x x x x 15 15 0 10 x
d2 x x x x 15 15 1 13 x
d3 x x x x 0 0 1 15 x
d4 x x x x 8 0 2 15 x 
module BSU_BISU_8_4 (EN, DI1, DI2, DI3, DI4, INV, clk, rst, DO1, DO2, DO3, DO4);
    input EN, INV, clk, rst;
    input [3:0] DI1, DI2, DI3, DI4;
    output [3:0] DO1, DO2, DO3, DO4;
    wire [3:0] a1, a2, a3, a4;
    wire [3:0] b1, b2, b3, b4;
    wire [3:0] c1, c2, c3, c4;
    wire [3:0] d1, d2, d3, d4;


    BSU4 B1(.in1(DI1), .in2(DI2), .in3(DI3), .in4(DI4), .out1(a1), .out2(a2), .out3(a3), .out4(a4));

    BISU B2(.EN(EN), .INV(INV), .rst(rst), .clk(clk), .DI1(a1), .DI2(a2), .DI3(a3), .DI4(a4), .DO1(b1), .DO2(b2), .DO3(b3), .DO4(b4));
    BISU B3(.EN(EN), .INV(INV), .rst(rst), .clk(clk), .DI1(b1), .DI2(b2), .DI3(b3), .DI4(b4), .DO1(c1), .DO2(c2), .DO3(c3), .DO4(c4));
    BISU B4(.EN(EN), .INV(INV), .rst(rst), .clk(clk), .DI1(c1), .DI2(c2), .DI3(c3), .DI4(c4), .DO1(d1), .DO2(d2), .DO3(d3), .DO4(d4));
    BISU B5(.EN(EN), .INV(INV), .rst(rst), .clk(clk), .DI1(d1), .DI2(d2), .DI3(d3), .DI4(d4), .DO1(DO1), .DO2(DO2), .DO3(DO3), .DO4(DO4));
endmodule


module BSU_BISU_8_4_test;
reg EN,INV,clk,rst;
reg [3:0] DI1,DI2,DI3,DI4;
wire [3:0] DO1,DO2,DO3,DO4;
wire [3:0]a1,a2,a3,a4;
wire [3:0]b1,b2,b3,b4;
wire [3:0]c1,c2,c3,c4;
wire [3:0]d1,d2,d3,d4;

BSU_BISU_8_4 B1 (EN,DI1,DI2,DI3,DI4,INV,clk,rst,DO1,DO2,DO3,DO4,a1,a2,a3,a4,b1,b2,b3,b4,c1,c2,c3,c4,d1,d2,d3,d4);

always #50 clk = ~clk;

initial 
    begin   
       clk = 1;     
        @(posedge clk);
              EN = 1; INV = 0; rst = 1;
        @(posedge clk); 
              DI1 = 4'b0010; //2
              DI2 = 4'b1101; //13
              DI3 = 4'b0001; //1
              DI4 = 4'b0101; //5
              rst = 0;
        @(posedge clk);
             DI1 = 4'b1000; //8
              DI2 = 4'b1010; //10
              DI3 = 4'b1111; //15
              DI4 = 4'b0001; //1
        @(posedge clk);
             DI1 = 4'b0000; //0
              DI2 = 4'b0000; //0
              DI3 = 4'b0000; //0
              DI4 = 4'b0000; //0
        @(posedge clk);           
              DI1 = 4'b1111; //15
              DI2 = 4'b1111; //15
              DI3 = 4'b1111; //15
              DI4 = 4'b1111; //15
        #300;
        $stop;
    end
endmodule


//Bitonic Sort Unit
module BSU4 (in1, in2, in3, in4, out1, out2, out3, out4);
    input [3:0] in1, in2, in3, in4;
    output [3:0] out1, out2, out3, out4;
    wire [3:0] a1, a2, a3, a4;
    wire [3:0] b1, b2, b3, b4;

    CULH C1 (.x(in1), .y(in2), .L(a1), .H(a2));
    CUHL C2 (.x(in3), .y(in4), .H(a3), .L(a4));
    CULH C3 (.x(a1), .y(a3), .L(b1), .H(b3));
    CULH C4 (.x(a2), .y(a4), .L(b2), .H(b4));
    CULH C5 (.x(b1), .y(b2), .L(out1), .H(out2));
    CULH C6 (.x(b3), .y(b4), .L(out3), .H(out4));
endmodule
     
        module CULH (x,y,L,H);
        input [3:0]x,y;
        output [3:0]L,H;
        reg sel;

        always @(*) begin
             if (x > y) begin
                  sel = 0;
             end else if (x == y) begin
                  sel = 0;
             end else begin
                  sel = 1;
             end
        end

        mux2_1 m1 (y,x,sel,L);
        mux2_1 m2 (x,y,sel,H);
        endmodule 

        module CUHL (x,y,H,L);
        input [3:0]x,y;
        output [3:0]H,L;
        reg sel;

        always @(*) begin
             if (x > y) begin
                  sel = 0;
             end else if (x == y) begin
                  sel = 0;
             end else begin
                  sel = 1;
             end
        end

        mux2_1 m1 (x,y,sel,H);
        mux2_1 m2 (y,x,sel,L);
        endmodule

//Bidirectional Insertional Sort Unit (BISU)
module BISU (EN, INV, rst, clk, DI1, DI2, DI3, DI4, DO1, DO2, DO3, DO4);
    input EN, INV, rst, clk;
    input [3:0] DI1, DI2, DI3, DI4;
    output [3:0] DO1, DO2, DO3, DO4;
    
    reg [3:0] Rd1, Rd2;
    wire INIT; 
    wire [3:0] RImin, RImax, ROmin, ROmax;
    wire [3:0] mux_out1, mux_out2;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            Rd1 <= 4'b1111;
            Rd2 <= 4'b0000;
        end else begin
            Rd1 <= mux_out1;
            Rd2 <= mux_out2;
        end
    end

    assign INIT = (!rst) ? (RImin > RImax) : INIT; // 1 - Recording Mode; 0 - Insertion mode.
    
 
    mux2_1 m1 (Rd1, Rd2, INV, RImin);
    mux2_1 m2 (Rd2, Rd1, INV, RImax);

    BISL B1 (.RImin(RImin), .DI1(DI1), .DI2(DI2), .DI3(DI3), .DI4(DI4), .RImax(RImax), .EN(EN), .INIT(INIT), .clk(clk), .ROmin(ROmin), .ROmax(ROmax), .DO1(DO1), .DO2(DO2), .DO3(DO3), .DO4(DO4));

    mux2_1 m3 (.d0(ROmin), .d1(ROmax), .s(INV), .d(mux_out1));
    mux2_1 m4 (.d0(ROmax), .d1(ROmin), .s(INV), .d(mux_out2));
endmodule

module BISL (RImin,DI1,DI2,DI3,DI4,RImax,EN,INIT,clk,ROmin,ROmax,DO1,DO2,DO3,DO4);
  input [3:0] RImin, RImax;
  input EN, INIT, clk;
  input [3:0] DI1, DI2, DI3, DI4;
  output reg [3:0] DO1, DO2, DO3, DO4;
  output [3:0] ROmin, ROmax;
  wire cmp1, cmp2;
  wire [3:0] mux1_out, mux2_out, mux4_out, mux5_out;
  wire [3:0] DO1_wire, DO2_wire, DO3_wire, DO4_wire;

  assign cmp1 = RImin > DI1;
  mux2_1 m1 (RImin, DI1, cmp1, mux1_out);
  mux2_1 m2 (mux1_out, DI1, INIT, mux2_out);
  mux2_1 m3 (RImin, mux2_out, EN, ROmin);

  SRL_1 S1 (EN, INIT, DI1, DI2, RImin, RImax, DI2, DO1_wire);
  SRL S2 (EN, INIT, DI1, DI2, DI3, RImin, RImax, RImin, DO2_wire);
  SRL S3 (EN, INIT, DI2, DI3, DI4, RImin, RImax, RImax, DO3_wire);
  SRL_P S4 (EN, INIT, DI3, DI4, RImin, RImax, DI3, DO4_wire);

  assign cmp2 = RImax < DI4;
  mux2_1 m4 (RImax, DI4, cmp2, mux4_out);
  mux2_1 m5 (mux4_out, DI4, INIT, mux5_out);
  mux2_1 m6 (RImax, mux5_out, EN, ROmax);
  
  always @(posedge clk)
  begin
        DO1 <= DO1_wire;
        DO2 <= DO2_wire;
        DO3 <= DO3_wire;
        DO4 <= DO4_wire;
    end     
endmodule

module SRL_1 (EN,INIT,Dk,Dkp1,RMIN,RMAX,Drec,DO);
    input EN,INIT;             
    input [3:0] Dk;    // DI[k]
    input [3:0] Dkp1;  // DI[k+1]
    input [3:0] RMIN;       
    input [3:0] RMAX;    
    input [3:0] Drec;        
    output [3:0] DO;       

    wire cmp1, cmp2, cmp3, cmp4; 
    wire [3:0] mux5_out, mux3_out, mux2_out;
    wire [1:0] sel3;              
        
    assign cmp2 = (Dk > RMIN);      
    assign cmp3 = (Dk < RMAX);      
    assign cmp4 = (Dkp1 < RMIN);    

    mux2_1 mux5 (RMIN,Dkp1,cmp4,mux5_out);
    assign sel3 = {cmp2, cmp3};  
    mux4_1 mux3 (Dk,mux5_out,RMAX,Dk,sel3,mux3_out);
    mux2_1 mux2 (mux3_out,Drec,INIT,mux2_out);
    mux2_1 mux1 (Dk,mux2_out,EN,DO);
endmodule

module SRL (EN,INIT,Dkm1,Dk,Dkp1,RMIN,RMAX,Drec,DO);
    input EN,INIT;             
    input [3:0] Dkm1;  // DI[k-1]
    input [3:0] Dk;    // DI[k]
    input [3:0] Dkp1;  // DI[k+1]
    input [3:0] RMIN;       
    input [3:0] RMAX;    
    input [3:0] Drec;        
    output [3:0] DO;       

    wire cmp1, cmp2, cmp3, cmp4; 
    wire [3:0] mux4_out, mux5_out, mux3_out, mux2_out;
    wire [1:0] sel3;              

    assign cmp1 = (Dkm1 > RMAX);     
    assign cmp2 = (Dk > RMIN);      
    assign cmp3 = (Dk < RMAX);      
    assign cmp4 = (Dkp1 < RMIN);    

    mux2_1 mux4 (RMAX,Dkm1,cmp1,mux4_out);
    mux2_1 mux5 (RMIN,Dkp1,cmp4,mux5_out);
    assign sel3 = {cmp2, cmp3};  
    mux4_1 mux3 (Dk,mux5_out,mux4_out,Dk,sel3,mux3_out);
    mux2_1 mux2 (mux3_out,Drec,INIT,mux2_out);
    mux2_1 mux1 (Dk,mux2_out,EN,DO);
endmodule

module SRL_P (EN,INIT,Dkm1,Dk,RMIN,RMAX,Drec,DO);
    input EN,INIT;             
    input [3:0] Dkm1;  // DI[k-1]
    input [3:0] Dk;    // DI[k]
    input [3:0] RMIN;       
    input [3:0] RMAX;    
    input [3:0] Drec;        
    output [3:0] DO;       

    wire cmp1, cmp2, cmp3, cmp4; 
    wire [3:0] mux4_out, mux3_out, mux2_out;
    wire [1:0] sel3;              

    assign cmp1 = (Dkm1 > RMAX);     
    assign cmp2 = (Dk > RMIN);      
    assign cmp3 = (Dk < RMAX);          

    mux2_1 mux4 (RMAX,Dkm1,cmp1,mux4_out);
    assign sel3 = {cmp2, cmp3};  
    mux4_1 mux3 (Dk,RMIN,mux4_out,Dk,sel3,mux3_out);
    mux2_1 mux2 (mux3_out,Drec,INIT,mux2_out);
    mux2_1 mux1 (Dk,mux2_out,EN,DO);
endmodule
verilog system-verilog
1个回答
0
投票

我尝试在两个不同的模拟器上编译您的代码，并且在两个模拟器上都出现相同的编译错误。 例如：

Error-[TMIPC] Many port connections 
  Too many module or UDP instance port connections:   
  Too many port connections are found for instance "B1" of module 
  "BSU_BISU_8_4"
  Source info: BSU_BISU_8_4 B1(EN, DI1, DI2, DI3, DI4, INV, clk, rst, DO1, 
  DO2, DO3, DO4, a1, a2, a3, a4, b1, b2, b3, b4, c1, c2, c3, c4, d1, d2, d3, 
  d4);

您需要使用不同的模拟器来检测此类错误。 在 EDA Playground 上尝试您的代码。

要修复该错误，您需要向 

BSU_BISU_8_4
模块添加更多模块端口，或者删除 
BSU_BISU_8_4 B1
实例中未使用的连接。

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