为什么即使在 vhdl 中使用正确的语法,我的编译器也无法识别数组?

问题描述 投票:0回答:1

我是一名数字技术学生,正在尝试学习 VHDL。

我为 4 位 bcd 加法器编写了此测试台代码到 7 段显示

我已经尝试了我和聊天GPT能想到的所有可能性,但编译器仍然给了我同样的错误

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BCD_Adder_7Segment_tb is
end BCD_Adder_7Segment_tb;

architecture Behavioral of BCD_Adder_7Segment_tb is

    -- Component declaration for the DUT (Design Under Test)
    component BCD_Adder_7Segment is
        Port (
            A, B : in BIT_VECTOR(3 downto 0);
            Cin : in BIT;
            Sum : out BIT_VECTOR(3 downto 0);
            Cout : out BIT;
            SEG_A, SEG_B, SEG_Sum : out STD_LOGIC_VECTOR(6 downto 0)
        );
    end component;

    -- Testbench signals
    signal A_tb, B_tb, Sum_tb : BIT_VECTOR(3 downto 0);
    signal Cin_tb, Cout_tb : BIT;
    signal SEG_A_tb, SEG_B_tb, SEG_Sum_tb : STD_LOGIC_VECTOR(6 downto 0);

   
         constant  TableArray : array (0 to 15) of STD_LOGIC_VECTOR (3 downto 0) := (
        "0000", "0001", "0010", "0011",
        "0100", "0101", "0110", "0111",
        "1000", "1001", "1010", "1011",
        "1100", "1101", "1110", "1111" );

begin

    -- Instantiate the DUT
    DUT : BCD_Adder_7Segment
        port map (
            A => A_tb,
            B => B_tb,
            Cin => Cin_tb,
            Sum => Sum_tb,
            Cout => Cout_tb,
            SEG_A => SEG_A_tb,
            SEG_B => SEG_B_tb,
            SEG_Sum => SEG_Sum_tb
        );

   -- Stimulus process
    stimulus_process: process
        variable F1 : bit;
    begin
        -- Initialize inputs
        A_tb <= "0000";
        B_tb <= "0000";
        Cin_tb <= '0';

        -- Test all possible combinations of A, B, and Cin
        for i in 0 to 15 loop
            for j in 0 to 15 loop
                for k in 0 to 1 loop
                    case k is
                        when 0 =>
                            F1 := '0';
                        when 1 =>
                            F1 := '1';
                    end case;

                    A_tb <=  TableArray (i);
                    B_tb <=  TableArray (j);
                    Cin_tb <= F1;

                    -- Apply stimulus
                    wait for 10 ns;
                end loop;
            end loop;
        end loop;

        wait;
    end process stimulus_process;

end Behavioral;

`

错误状态

vcom -work work -2002 -explicit -stats=none F:/Softwares/BCD_Adder_7Segment_tb.vhd 模型技术 ModelSim - 英特尔 FPGA 版 vcom 2021.1 编译器 2021.02 2021 年 2 月 3 日 -- 加载标准包 -- 加载 TEXTIO 包 -- 加载包std_logic_1164 -- 编译实体BCD_Adder_7Segment_tb -- BCD_Adder_7Segment_tb 的编译架构行为 ** 错误:F:/Softwares/BCD_Adder_7Segment_tb.vhd(26):靠近“array”:(vcom-1576) 需要 STRING 或 IDENTIFIER 或 << or '('. ** Error: F:/Softwares/BCD_Adder_7Segment_tb.vhd(67): (vcom-1136) Unknown identifier "TableArray". ** Error: F:/Softwares/BCD_Adder_7Segment_tb.vhd(68): (vcom-1136) Unknown identifier "TableArray". ** Note: F:/Softwares/BCD_Adder_7Segment_tb.vhd(80): VHDL Compiler exiting

所以显然我的数组无法被识别,我不明白为什么会这样

vhdl fpga modelsim
1个回答
0
投票

您需要先创建一个类型:

         type TableArrayType is array (0 to 15) of STD_LOGIC_VECTOR (3 downto 0) ; 

         constant  TableArray : TableArrayType := (
        "0000", "0001", "0010", "0011",
        "0100", "0101", "0110", "0111",
        "1000", "1001", "1010", "1011",
        "1100", "1101", "1110", "1111" );

© www.soinside.com 2019 - 2024. All rights reserved.