`timescale 1ns / 1ps
module pc_reg(
input wire clk,
input wire rst,
input wire stall,
input wire [`AddrLen - 1 : 0] jmp_target,
input wire jmp_enable,
input wire [`AddrLen - 1 : 0] prediction,
input wire pred_enable,
output reg [`AddrLen - 1 : 0] pc,
output reg enable_pc
);
reg [`AddrLen - 1 : 0] npc;
reg assigned;
always @ (posedge clk) begin
if (rst == `ResetEnable) begin
pc <= `ZERO_WORD;
npc <= 4;
assigned <= 1'b0;
enable_pc <= 1'b1;
end
else begin
if (jmp_enable == `JumpEnable) begin
....
end
else if (pred_enable == `JumpEnable && assigned != 1'b1) begin
....
end
else if (stall == `StallDisable) begin
pc <= npc;
npc <= npc + 4;
assigned <= 1'b0;
enable_pc <= 1'b1;
end
else begin
enable_pc <= 1'b0;
end
end
end
endmodule
这段代码的预期功能是在每个周期将4添加到npc。
[如果您仔细看,您会发现波形显示将npc显示为[30:0](因此它不显示[31:0],它应为32位宽)。