system verilog虚函数继承问题

Question

代码如下

module virtual_method;

    // this example is refered to the lab1 class inheritance
    // the propuse is to learn the convinience of the virtual method 
class trans;

    bit[31:0] data;
    int pkt_id;
    int data_nidles;
    int pkt_nidles;
    bit rsp;
    string name;
    virtual function trans clone(trans t = null);
    
        if (t == null)
                t = new();
        t.data = data;
        t.pkt_id = pkt_id;
        t.data_nidles = data_nidles;
        t.pkt_nidles= pkt_nidles;
        t.rsp = rsp;
        return t;
    endfunction

    virtual function print_f(int i,  name = "tr");
        $display("this is trans class i = %d,name = %s",i,name);
    endfunction
endclass

class ch_trans extends trans;

    int ch_id;
    string name;
    virtual function trans clone(trans t = null);
        ch_trans ct;    
        if (t == null)
            ct = new();
        else
            void'($cast(ct,t));
        ct.ch_id = ch_id;
        return ct;
    endfunction

    virtual function print_f(int i, name = "ch_trans");

        $display("this is ch_trans class i = %d name =%s ",i,name);
    endfunction
endclass


initial begin
    trans t1,t2;
    ch_trans ct1,ct2;
    
    ct1 = new();
    ct1.pkt_id = 2;
    ct1.ch_id = 3;
    $display("ct1 = %p",ct1);
    
    t1 = ct1; 
    t1.print_f(7);
end

endmodule

很困惑为什么 t1.print(7) 函数为什么 print name = "tr" 而不是 "ch_trans"？

我在vcs调试发现t1.print_f(7)调用子类print_f函数没有调用类tans print_f函数

我认为这个打印“ch_trans”；但它没有。