我正在尝试在 Quartus II 中运行此 Verilog 代码,但因为它不起作用。
module verilog_qs(
input wire clk,
input wire [10:0] in1, in2, in3, in4, in5, in6, in7, in8, in9, in10,
output reg [10:0] out1, out2, out3, out4, out5, out6, out7, out8, out9, out10
);
reg signed [10:1] data [0:10];
function automatic integer partition;
input integer l, h;
integer pivot;
integer left_wall;
integer i;
integer temp;
begin
pivot = data[h];
left_wall = l - 1;
for (i = l; i < h; i = i + 1)
begin
if (data[i] < pivot)
begin
left_wall = left_wall + 1;
temp = data[i];
data[i] = data[left_wall];
data[left_wall] = temp;
end
end
temp = data[h];
data[h] = data[left_wall + 1];
data[left_wall + 1] = temp;
partition = left_wall + 1;
end
endfunction
function automatic integer qs;
input integer low, high;
integer pivot;
integer stack[0:10]; // Stack to store indices
integer top;
integer part_index;
integer ignored;
begin
top = 0;
stack[top] = low;
top = top + 1;
stack[top] = high;
while (top >= 0)
begin
high = stack[top];
top = top - 1;
low = stack[top];
top = top - 1;
if (low < high)
begin
part_index = partition(low, high);
top = top + 1;
stack[top] = low;
top = top + 1;
stack[top] = part_index - 1;
top = top + 1;
stack[top] = part_index + 1;
top = top + 1;
stack[top] = high;
end
end
qs = 0;
end
endfunction
integer ignored;
always @(posedge clk) begin
data[1] = in1;
data[2] = in2;
data[3] = in3;
data[4] = in4;
data[5] = in5;
data[6] = in6;
data[7] = in7;
data[8] = in8;
data[9] = in9;
data[10] = in10;
ignored = qs(1, 10);
out1 = data[1];
out2 = data[2];
out3 = data[3];
out4 = data[4];
out5 = data[5];
out6 = data[6];
out7 = data[7];
out8 = data[8];
out9 = data[9];
out10 = data[10];
end
endmodule
我尝试使用 while 循环,但这不起作用。
当在代码中递归调用函数并且编译器(在本例中为 RTL 工具)必须展开整个递归调用以便能够从中构建前向传播网表时,就会发生此错误。现在这个错误有两个原因:
low < high
一直评估为 true,那么递归调用将永远不会结束。您有两种方法,如果您相信递归最终会收敛,则尝试增加迭代次数,或者找出导致无限递归的错误。