如何在vivado中同一个周期写入12个地址并且仍然被识别为BRAM

Question

这是原始代码，被合成为BRAM

module RAM_IMAGINARY (clk, we, en, addr, di, dout);
input clk;
input we;
input en;
input [7:0] addr;
input [15:0] di;
output [15:0] dout;
logic [15:0] RAM_IMAGINARY [167:0];
logic [15:0] dout;
always @(posedge clk)
begin
if (en)begin
if (we) begin
  RAM_IMAGINARY[addr] <= di;
  dout <= di;
end
else
dout <= RAM_IMAGINARY[addr];
end
end
endmodule      

我想在一个周期内在内存中写入一整列，想象一下这个RAM是12x14。

我还尝试像这样实例化每个模块中的 12 个中的一个，但由于宽度和深度较小，它们未被识别为 BRAM。

       module RAM_IMAGINARY (clk, we, en, addr, di, dout);
       input clk;
       input we;
       input en;
       input [7:0] addr;
       input [15:0] di;
       output [15:0] dout;
       logic [15:0] RAM_IMAGINARY [13:0];
       logic [15:0] dout;
       always @(posedge clk)
       begin
       if (en)begin
       if (we) begin
       RAM_IMAGINARY[addr] <= di;
       dout <= di;
       end
       else
       dout <= RAM_IMAGINARY[addr];
       end
       end
       endmodule

    module Top(clk, we, en, addr, di, dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8,dout9,dout10,dout11);
    input clk;
    input we;
    input en;
    input [7:0] addr;
    input [15:0] di;
    output [15:0] dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8,dout9,dout10,dout11;
    RAM_IMAGINARY RAM0 (clk, we, en, addr, di, dout0) ;
    RAM_IMAGINARY RAM1 (clk, we, en, addr, di, dout1) ;
    RAM_IMAGINARY RAM2 (clk, we, en, addr, di, dout2) ;
    RAM_IMAGINARY RAM3 (clk, we, en, addr, di, dout3) ;
    RAM_IMAGINARY RAM4 (clk, we, en, addr, di, dout4) ;
    RAM_IMAGINARY RAM5 (clk, we, en, addr, di, dout5) ;
    RAM_IMAGINARY RAM6 (clk, we, en, addr, di, dout6) ;
    RAM_IMAGINARY RAM7 (clk, we, en, addr, di, dout7) ;
    RAM_IMAGINARY RAM8 (clk, we, en, addr, di, dout8) ;
    RAM_IMAGINARY RAM9 (clk, we, en, addr, di, dout9) ;
    RAM_IMAGINARY RAM10 (clk, we, en, addr, di, dout10) ;
    RAM_IMAGINARY RAM11 (clk, we, en, addr, di, dout11) ;
    
        
    endmodule

这是我的代码，是vivado指南中的典型BRAM代码，我想一次写入一整列，想象它是一个12x14内存。我尝试实例化 12 个 RAM，并在同一周期写入每个 RAM，但由于深度和宽度较小，它没有被识别为 BRAM。帮助

我尝试在同一周期写入12个地址

Answer 1

我在内存模型中的内存变量中添加了一个ram_style属性。
这就是该工具所需的提示。

module RAM_IMAGINARY (clk, we, en, addr, di, dout);
  input clk;
  input we;
  input en;
  input [7:0] addr;
  input [15:0] di;
  output [15:0] dout;
  logic [15:0] dout;

(* ram_style = “block” *) logic [15:0] RAM_IMAGINARY [13:0];

always @(posedge clk)
begin
  if (en)begin
  if (we) begin
  RAM_IMAGINARY[addr] <= di;
  dout <= di;
  end
  else
  dout <= RAM_IMAGINARY[addr];
  end
end

endmodule

我使用了你的顶级模块，没有任何改变

    module Top(clk, we, en, addr, di, dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8,dout9,dout10,dout11);
    input clk;
    input we;
    input en;
    input [7:0] addr;
    input [15:0] di;
    output [15:0] dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8,dout9,dout10,dout11;
    RAM_IMAGINARY RAM0 (clk, we, en, addr, di, dout0) ;
    RAM_IMAGINARY RAM1 (clk, we, en, addr, di, dout1) ;
    RAM_IMAGINARY RAM2 (clk, we, en, addr, di, dout2) ;
    RAM_IMAGINARY RAM3 (clk, we, en, addr, di, dout3) ;
    RAM_IMAGINARY RAM4 (clk, we, en, addr, di, dout4) ;
    RAM_IMAGINARY RAM5 (clk, we, en, addr, di, dout5) ;
    RAM_IMAGINARY RAM6 (clk, we, en, addr, di, dout6) ;
    RAM_IMAGINARY RAM7 (clk, we, en, addr, di, dout7) ;
    RAM_IMAGINARY RAM8 (clk, we, en, addr, di, dout8) ;
    RAM_IMAGINARY RAM9 (clk, we, en, addr, di, dout9) ;
    RAM_IMAGINARY RAM10 (clk, we, en, addr, di, dout10) ;
    RAM_IMAGINARY RAM11 (clk, we, en, addr, di, dout11) ;
    
        
    endmodule

参见UG901 P49

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综合后原理图和利用率报告如下所示。